Low Power V.22 bis Modem
CMX868
The FSK demodulator recognises individual frequencies as representing received ‘1’ or ‘0’ data bits:
The QAM/DPSK demodulator decodes QAM or DPSK modulation of a 1200Hz or 2400Hz carrier and is
used for V.22, V.22 bis and Bell 212A modes. It includes an adaptive receive signal equaliser (auto-
equaliser) that will automatically compensate for a wide range of line conditions in both QAM and DPSK
modes. It must be enabled when receiving 2400bps QAM. The auto-equaliser can provide a useful
improvement in performance in 600 or 1200bps DPSK modes as well as 2400bps QAM, so although it
must be disabled at the start of a handshake sequence, it can be enabled as soon as scrambled 1200bps
1s have been detected.
Both FSK amd QAM/DPSK demodulators produce a serial data bit stream which is fed to the Rx pattern
detector, descrambler and USART block, See Figure 8a. In QAM/DPSK modes the demodulator input is
also monitored for the V.22 bis handshake ‘S1’ signal.
The QAM/DPSK demodulator also estimates the received bit error rate by comparing the actual received
signal against an ideal waveform. This estimate is placed in bits 2-0 of the Status Register, see Figure
11.
1.5.8 Rx Modem Pattern Detectors and Descrambler
See Figure 8a.
The 1010.. pattern detector operates only in FSK modes and will set bit 9 of the Status Register when 32
bits of alternating 1’s and 0’s have been received.
The ‘Continuous Unscrambled 1’s’ detector operates in all modem modes and sets bits 8 and 7 of the
Status Register to ‘01’ when 32 consecutive 1’s have been received.
The descrambler operates only in DPSK/QAM modes and is enabled by setting bit 7 of the Rx Mode
Register.
The ‘Continuous Scrambled 1’s’ detector operates only in DPSK/QAM modes when the descrambler is
enabled and sets bits 8 and 7 of the Status Register to ‘11’ when 32 consecutive 1’s appear at the output
of the descrambler. To avoid possible ambiguity, the ‘Scrambled 1’s’ detector is disabled when
continuous unscrambled 1’s are detected.
The ‘Continuous 0’s’ detector sets bits 8 and 7 of the Status Register to ‘10’ when NX consecutive 0’s
have been received, NX being 32 except when DPSK/QAM Start-Stop mode has been selected, in which
case NX = 2N + 4 where N is the number of bits per character including the Start, Stop and any Parity
bits.
All of these pattern detectors will hold the ‘detect’ output for 12 bit times after the end of the detected
pattern unless the received bit rate or operating mode is changed, in which case the detectors are reset
within 2 msec.
1.5.9 Rx Data Register and USART
A flexible Rx USART is provided for all modem modes, meeting the requirements of V.14 for QAM and
DPSK modems. It can be programmed to treat the received data bit stream as Synchronous data or as
Start-Stop characters.
In Synchronous mode the received data bits are all fed into the Rx Data Buffer which is copied into the
C-BUS Rx Data Register after every 8 bits.
In Start-Stop mode the USART Control logic looks for the start of each character, then feeds only the
required number of data bits (not parity) into the Rx Data Buffer. The parity bit (if used) and the presence
ã 2004 CML Microsystems Plc
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D/868/9
CMLMICRO [ CML MICROCIRCUITS ]
