FSK Modem and DTMF Codec
CMX865
5.10.7 Status Register
Status Register: 16-bit read-only.
C-BUS address $E6
All the bits of this register (except b15-14) are cleared to 0 by a General Reset command, or when b7
(Reset) of the General Control Register is 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
IRQ
RD
PF
See below for uses of these bits
The meanings of the Status Register b12-0 depend on whether the receive circuitry is in Modem or Tones
Detect mode.
Status Register bits:
Rx Modem modes
Rx Tones Detect modes
** IRQ
Mask bit
b15
b14
b13
b12
IRQ
Set to 1 on Ring Detect
Programming Flag bit. See 5.10.8
b5
b4
b3
Set to 1 on Tx data ready.
Cleared by write to Tx Data Register
b11
b10
Set to 1 on Tx data underflow.
Cleared by write to Tx Data Register
1 when energy is detected in Rx 1 when energy is detected in Call
b3
b2
modem signal band
Progress band or when both
programmable tones are detected
b9
b8
b7
1 when ‘1010..’ pattern is detected
1 when continuous 0s detected
1 when continuous 1s detected
0
0
b1
b1
b1
1 when 2100Hz answer tone or the
second programmed tone is
detected
b6
b5
Set to 1 on Rx data ready. Cleared 1 when 2225Hz answer tone or the
by read from Rx Data Register first programmed tone is detected
Set to 1 on Rx data overflow. 1 when DTMF code is detected
b0
b0
Cleared by read from Rx Data
Register
b4
b3
b2
b1
b0
Set to 1 on Rx framing error
Set to 1 on even Rx parity
0
0
0
-
-
-
-
-
Rx DTMF code b3, see table
Rx DTMF code b2
Rx DTMF code b1
FSK frequency demodulator output Rx DTMF code b0
Notes: ** This column shows the corresponding IRQ Mask bits in the General Control Register. A 0-to-1
transition on any of the Status Register b14-5 will cause the IRQ b15 to be set to 1 if the
corresponding IRQ Mask bit is 1. The IRQ bit is cleared by a read of the Status Register or a
General Reset command or by setting b7 or b8 of the General Control Register to 1.
The operation of the data demodulator and pattern detector circuits within the CMX865 does not
depend on the state of the Rx energy detect function.
© 2005 CML Microsystems Plc
26
D/865/3
CMLMICRO [ CML MICROCIRCUITS ]
