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CMX865D2 参数 Datasheet PDF下载

CMX865D2图片预览
型号: CMX865D2
PDF下载: 下载PDF文件 查看货源
内容描述: FSK调制解调器和DTMF编解码器 [FSK Modem and DTMF Codec]
分类和应用: 解码器调制解调器编解码器电信集成电路电信电路光电二极管
文件页数/大小: 42 页 / 1293 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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FSK Modem and DTMF Codec  
CMX865  
5.10.2 General Control Register  
General Control Register: 16-bit write-only. C-BUS address $E0  
This register controls general features of the CMX865 such as the Powersave and Loopback modes, the  
IRQ mask bits and the Relay Drive output. It also allows the fixed compromise equalisers in the Tx and Rx  
signal paths to be disabled if desired, and sets the internal clock dividers to use either a 11.0592 or a  
12.288 MHz XTAL frequency.  
All bits of this register are cleared to 0 by a General Reset command.  
15  
0
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Bit:  
TXA TXAN Xtal  
off off freq  
LB  
Equ  
Rly  
drv  
Pwr  
Rst  
Irqn  
en  
IRQ Mask Bits  
General Control Register b15: Reserved, set to 0  
General Control Register b14: Disconnect TXA Output  
This bit allows the TXA output to be disconnected and set to high impedance.  
b14 = 1  
b14 = 0  
TXA output disconnected.  
TXA output connected (normal modem operation).  
General Control Register b13: Disconnect TXAN Output  
This bit allows the TXAN output to be disconnected and set to high impedance.  
b13 = 1  
b13 = 0  
TXAN output disconnected.  
TXAN output connected (normal modem operation).  
General Control Register b12: Xtal Frequency  
This bit should be set according to the Xtal frequency.  
b12 = 1  
b12 = 0  
11.0592MHz  
12.2880MHz  
General Control Register b11: Analogue Loopback Test Mode  
This bit controls the analogue loopback test mode. Note that in loopback test mode both Transmit  
and Receive Mode Registers should be set to the same modem type and band or bit rate.  
b11 = 1  
b11 = 0  
Local analogue loopback mode enabled  
No loopback (normal modem operation)  
General Control Register b10: Tx and Rx Fixed Compromise Equalisers  
This bit allows the Tx and Rx fixed compromise equalisers in the modem transmit and receive  
filter blocks to be disabled.  
b10 = 1  
b10 = 0  
Disable equalisers  
Enable equalisers (1200bps modem modes)  
General Control Register b9: Relay Drive  
This bit directly controls the RDRVN output pin.  
b9 = 1  
b9 = 0  
RDRVN output pin pulled to VSS  
RDRVN output pin pulled to VDD  
© 2005 CML Microsystems Plc  
18  
D/865/3  
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