CMX7261 Voice Multi-transcoder
CMX7261
64-pin
Q1/L9
Pin
Signal Description
Pin No.
Name
Type
PWR
3.3V positive supply rail for the digital on-chip circuits. This
pin should be decoupled to DVSS by capacitors mounted
close to the supply pins.
45
DVDD3V3
46
47
48
49
NC
NC
Do not connect.
DVSS
DVSS
XTALN
PWR
PWR
OP
Negative supply rail (ground) for the digital on-chip circuits.
Negative supply rail (ground) for the digital on-chip circuits.
Output of the on-chip xtal oscillator inverter.
Input to the oscillator inverter from the xtal circuit or external
clock source.
50
XTAL/CLOCK
IP
51
52
53
NC
NC
NC
IP
Do not connect.
NC
Do not connect.
SCLK
C-BUS serial clock input from the µC.
3-state C-BUS serial data output to the µC. This output is
high impedance when not sending data to the µC.
54
RDATA
TS OP
55
56
CDATA
CSN
IP
IP
C-BUS serial data input from the µC.
C-BUS chip select input from the µC.
‘wire-Orable’ output for connection to the Interrupt Request
input of the µC. This output is pulled down to DVSS when
active and is high impedance when inactive. An external
pull-up resistor is required.
57
IRQN
OP
Digital core supply, nominally 1.8V. Normally this will be
supplied by the on-chip regulator, although an option is
available to use an external regulator. This pin should be
decoupled to DVSS by capacitors mounted close to the
device pins and connected with a power supply track to
DVCORE1. For details see programming register P1.19 in
section in 10.1.2 Program Block 1 – Clock Control.
58
DVCORE2
PWR
While booting FI:
SPI: Master Out Slave In (MOSI).
While running FI:
PCM: Serial Data Out.
59
60
61
62
63
64
SDO
FSO
OP
OP
IP
PCM: Frame Sync Out.
While booting FI:
SPI: Master In Slave Out (MISO).
While running FI:
SDI
PCM: Serial Data In.
SSOUT0
CLKO
FSI
OP
OP
BI
SPI: Slave Select Out 0.
While booting FI:
SPI: Serial Clock (SCLK).
While running FI:
PCM: Serial Clock Out.
PCM: Frame Sync In.
2012 CML Microsystems Plc
Page 11
D/7261_FI-1.x/9
CMLMICRO [ CML MICROCIRCUITS ]
