CMX7261 Voice Multi-transcoder
CMX7261
64-pin
Q1/L9
Pin
Signal Description
Pin No.
Name
ANAIN2P
Type
Input (IP) and feedback (FB) connections to single ended
audio input 2. Gain and filtering circuitry can be constructed
around these pins. Together these are referred to as
ANAIN2.
23
24
IP
ANAIN2FB
OP
25
26
NC
NC
NC
NC
Do not connect.
Do not connect.
Internally generated bias voltage of approximately AVDD/2.
If VBIAS is power saved this pin will present a high
impedance to AVDD. This pin must be decoupled to AVSS
by a capacitor mounted close to the device pins; no other
connections should be made.
27
VBIAS
OP
28
29
30
31
32
33
34
35
36
ANAINP
ANAINN
ADCREF
NC
IP
IP
Differential inputs for main audio; ‘P’ is positive, ‘N’ is
negative. Together these are referred to as the ANAIN.
ADC reference voltage; connect to AVSS.
Do not connect.
NC
NC
NC
NC
NC
NC
NC
Do not connect.
NC
Do not connect.
NC
Do not connect.
NC
Do not connect.
NC
Do not connect.
Positive 3.3V supply rail for the analogue on-chip circuit.
Levels and thresholds within the device are proportional to
this voltage. This pin should be decoupled to AVSS by
capacitors mounted close to the device pins.
37
AVDD
PWR
Negative supply rail (ground) for the analogue on-chip
circuits.
38
AVSS
PWR
39
40
41
42
43
NC
NC
Do not connect.
NC
NC
Do not connect.
NC
NC
Do not connect.
NC
NC
Do not connect.
DVSS
PWR
Negative supply rail (ground) for the digital on-chip circuits.
Digital core supply, nominally 1.8V. By default this will be
supplied by an on-chip regulator, although an option is
available to use an external regulator. This pin should be
decoupled to DVSS by capacitors mounted close to the
device pins and connected with a power supply track to
DVCORE2. For details see programming register P1.19 in
section in 10.1.2 Program Block 1 – Clock Control.
44
DVCORE1
PWR
2012 CML Microsystems Plc
Page 10
D/7261_FI-1.x/9
CMLMICRO [ CML MICROCIRCUITS ]
