CMX7163 QAM Modem
CMX7163
64-pin
Q1/L9
Signal
Description
Pin No.
51
Name
Type
OP
SYSCLK1
SYSCLK2
SCLK
Synthesised digital clock output 1
Synthesised digital clock output 2
C-BUS serial clock input from the µC
52
OP
IP
53
3-state C-BUS serial data output to the µC. This output is
high impedance when not sending data to the µC.
54
RDATA
TS OP
55
56
CDATA
CSN
IP
IP
C-BUS serial data input from the µC
C-BUS chip select input from the µC
‘wire-Orable’ output for connection to the Interrupt Request
input of the µC. This output is pulled down to DVSS when
active and is high impedance when inactive. An external
pull-up resistor is required.
57
IRQN
OP
Digital core supply, nominally 1.8V. Normally this will be
supplied by the on-chip regulator, although an option is
available to use an external regulator. This pin should be
decoupled to DVSS by capacitors mounted close to the
device pins. For details see programming register P1.19 in
section in 10.2.3 Program Block 1 – Clock Control.
58
DVCORE
PWR
59
60
61
62
63
64
MOSI
OP
OP
IP
SPI: Master Out Slave In
SPI: Slave Select Out 1
SPI: Master In Slave Out
SPI: Slave Select Out 0
SPI: Serial Clock
SSOUT1
MISO
SSOUT0
CLK
OP
OP
BI
GPIOA
General Purpose I/O
On this device, the central metal pad (which is exposed on the Q1
package only) may be electrically unconnected or,
alternatively, may be connected to Analogue Ground (AVss).
EXPOSED
METAL PAD
SUBSTRATE
~
No other electrical connection is permitted.
Notes: IP
=
Input (+ PU/PD = internal pull-up / pull-down resistor of approximately 75kΩ)
OP
BI
TS OP
PWR
NC
=
=
=
=
=
Output
Bidirectional
3-state Output
Power Connection
No Connection - should NOT be connected to any signal
2014 CML Microsystems Plc
Page 13
D/7163_FI-4.x/12
CMLMICRO [ CML MICROCIRCUITS ]
