CMX7163 QAM Modem
CMX7163
64-pin
Q1/L9
Signal
Description
Pin No.
Name
Type
Internally generated bias voltage of approximately AVDD/2.
If VBIAS is powersaved this pin will be connected via a high
impedance to AVDD. This pin must be decoupled to AVSS
by a capacitor mounted close to the device pins.
27
VBIAS
OP
28
29
30
31
32
33
34
35
36
IINPUTP
IP
IP
Differential inputs for I channel signals; ‘P’ is positive, ‘N’ is
negative. Together these are referred to as the I Input.
IINPUTN
ADCREF
QINPUTP
QINPUTN
AUXADC1
AUXADC2
AUXADC3
AUXADC4
ADC reference voltage; connect to AVSS
IP
IP
IP
IP
IP
IP
Differential inputs for Q channel signals; ‘P’ is positive, ‘N’ is
negative. Together these are referred to as the Q Input.
Auxiliary ADC input 1
Auxiliary ADC input 2
Auxiliary ADC input 3
Auxiliary ADC input 4
Positive 3.3V supply rail for the analogue on-chip circuit.
Levels and thresholds within the device are proportional to
this voltage. This pin should be decoupled to AVSS by
capacitors mounted close to the device pins.
37
AVDD
PWR
Negative supply rail (ground) for the analogue on-chip
circuits.
38
AVSS
PWR
39
40
41
42
43
AUXDAC1
AUXDAC2
AUXDAC3
AUXDAC4
DVSS
OP
Auxiliary DAC output 1 (Optionally the RAMDAC output)
Auxiliary DAC output 2
OP
OP
Auxiliary DAC output 3
OP
Auxiliary DAC output 4
PWR
Negative supply rail (ground) for the digital on-chip circuits
Digital core supply, nominally 1.8V. By default this will be
supplied by an on-chip regulator, although an option is
available to use an external regulator. This pin should be
decoupled to DVSS by capacitors mounted close to the
device pins. For details see programming register P1.19 in
section in 10.2.3 Program Block 1 – Clock Control.
44
DVCORE
DVDD3V3
PWR
PWR
3.3V positive supply rail for the digital on-chip circuits. This
pin should be decoupled to DVSS by capacitors mounted
close to the supply pins.
45
46
47
48
49
NC
NC
Do not connect
NC
NC
May also be connected to DVSS
DVSS
XTALN
PWR
OP
Negative supply rail (ground) for the digital on-chip circuits
Output of the on-chip Xtal oscillator inverter
Input to the oscillator inverter from the Xtal circuit or
external clock source
50
XTAL/CLOCK
IP
2014 CML Microsystems Plc
Page 12
D/7163_FI-4.x/12
CMLMICRO [ CML MICROCIRCUITS ]
