CMX7163 QAM Modem
CMX7163
There are three complications to this process:
1. The total gain of the feedback loop I Output to CMX998 DCMEAS Error signal to AuxADC is
unknown – so the adjustment to the I Output signal may not be calculated completely accurately
from a single measurement. Therefore the gain applied to the calculated adjustment may be
programmed and a number of iterations selected, resulting in a damped feedback loop.
2. The dc error to be corrected is usually large enough that if measured with the CMX998 in high
gain mode the DCMEAS output would saturate. This makes calculation of the magnitude of error
impossible. Therefore low gain mode should be used initially.
3. When changing from low to high gain modes the circuit changes (see dc calibration Application
Note referenced earlier), therefore the correction needed changes. However the low gain
correction should at least be close to bringing the high gain measurement out of saturation. The
relationship between correction computed using low gain and high gain is consistent – so may be
noted and applied as an offset.
The calibration sequence implemented in the CMX7163 has the following stages:
Setup
RefI
Initialise the SSP port, AuxADC and select RefI as DCMEAS output from the CMX998
Read RefI, select DCMEAS = RefQ
RefQ
Read RefQ, select DCMEAS = ErrorI
ErrorILo
ErrorQLo
Read ErrorI assuming Low gain and adjust the I Output accordingly
Read ErrorQ assuming Low gain and adjust the Q Output accordingly
Iterate – go to ErrorILo after a delay for corrected signals to settle
Select High gain mode of the CMX998, apply Low to High gain mode correction
Read ErrorQ assuming High gain and adjust the Q Output accordingly
Read ErrorI assuming High gain and adjust the I Output accordingly
Iterate – go to ErrorQHi after a delay for corrected signals to settle
Restore the CMX998, to its stage pre-calibration – ready to output modulation
HighGain
ErrorQHi
ErrorIHi
Tidyup
Note: Despite no modulation being produced, the Tx Done flag of IRQ Status - $7E read register will be
set at the completion of the CMX998 DC Offset Calibration task.
The timings of each calibration step can be configured using
P4.8: Set legacy timing mode
b0
b1
ADC Sample
Delay
0 - minimal delay mode (gives a delay of 1.2 symbol times)
1 - legacy delay mode (gives a delay of 8.2 symbol times)
Tx Done and
Tx Last Tail
indication
timing
0-Selects minimal jitter of +/-0.6 symbol times for Tx Done and Tx Last Tail
indication timing.
Enables the use of the P4.9 delay adjustment control for Tx Done and Tx
Last Tail indication timing. Adjusting these delays enables indication timing to
be changed to better match any changes in Tx pulse shaping filter delay or
for other user purposes.
1-legacy timing delay mode (delay not specified; delay and jitter behaviours will
be consistent so long as the number of data field symbols, number of tail
symbols, and other factors are not changed)
b2-15
Reserved
Reserved – set to 1
P4.9: Set Tx Done delay
2014 CML Microsystems Plc
Page 36
D/7163_FI-4.x/12
CMLMICRO [ CML MICROCIRCUITS ]
