Marine AIS SART Processor
CMX7045
7
Detailed Description
7.1 Clock Source
The CMX7045 can be used with either a 9.6MHz xtal or a 19.2MHz oscillator.
7.2 Host Interface
This section provides a general description of the C-BUS serial interface protocol used to transfer data,
control and status information between the CMX7045 and its host.
C-BUS is a serial interface, similar to SPI, that uses a simple transaction-oriented command/response
protocol with addressing to access specific registers within the CMX7045. Each C-BUS transaction
consists of a single Register Address/Command byte (A/C byte) sent from the µC which may be followed
by one or more data byte(s) sent from the µC to be written into one of the CMX7045’s Write Only
registers, or one or more data byte(s) read out from one of the CMX7045’s Read Only registers, as
illustrated in Figure 4.
Data sent from the µC on the CDATA line is clocked into the CMX7045 on the rising edge of the SCLK
input. RDATA sent from the CMX7045 to the µC is valid when the SCLK is high. The CSN line must be
held low during a data transfer and kept high between transfers. The C-BUS interface is compatible with
most common µC serial interfaces and may also be easily implemented with general purpose µC I/O pins
controlled by a simple software routine.
The number of data bytes following an A/C byte is dependent on the value of the A/C byte. The most
significant bit of the address or data is sent first. For detailed timings see section 8.2.
C-BUS Write:
See Note 1
See Note 2
CSN
SCLK
CDATA
7
MSB
6
5
4
3
2
1
0
LSB
7
MSB
6
…
0
LSB
7
MSB
…
0
LSB
Address / Command byte
Upper 8 bits
Lower 8 bits
RDATA
High Z state
C-BUS Read:
See Note 2
CSN
SCLK
CDATA
7
MSB
6
5
4
3
2
1
0
LSB
Address byte
Upper 8 bits
Lower 8 bits
RDATA
7
MSB
6
…
0
LSB
7
MSB
…
0
LSB
High Z state
Data value unimportant
Repeated cycles
Either logic level valid
Figure 4 C-BUS Transactions
Notes:
1. For Command byte transfers only the first 8 bits are transferred.
2. For single byte data transfers only the first 8 bits of the data are transferred.
3. The CDATA and RDATA lines are never active at the same time. The Address byte determines the data
direction for each C-BUS transfer.
4. The SCLK input can be high or low at the start and end of each C-BUS transaction.
5. The gaps shown between each byte on the CDATA and RDATA lines in the above diagram are optional, the
host may insert gaps or concatenate the data as required.
2013 CML Microsystems Plc
12
D/7045FI-1.x/4
CMLMICRO [ CML MICROCIRCUITS ]
