Marine AIS SART Processor
CMX7045
5
PCB Layout Guidelines and Power Supply Decoupling
DVDD
Digital Ground Plane
+
C20 C21 C22
DVSS
DVSS
C3
DVSS
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
AVSS
AVDD
3
4
AVSS
AVDD
5
6
CMX7045Q3
DVSS
VDEC
+
C17 C18 C19
7
DVSS
8
9
AVSS
+
C24
C23
10
11
12
VBIAS
DVSS
C7
13 14 15 16 17 18 19 20 21 22 23 24
AVSS
Analogue Ground Plane
DVSS
AVSS
Figure 3 Power Supply Connections and De-coupling
Component values as per Table 2.
Notes:
1. The supply decoupling capacitors should be as close as possible to the CMX7045. It is therefore
recommended that the printed circuit board is laid out with separate ground planes for the AV and DV
SS
SS
supplies in the area of the CMX7045, with provision to make links between them, close to the CMX7045.
Use of a multi-layer printed circuit board will facilitate the provision of ground planes on separate layers.
2. The central metal pad on the ‘Q3’ package may be electrically unconnected or, alternatively, may be
connected to Analogue Ground (AV ). No other electrical connection is permitted.
SS
3.
V
is used as an internal reference for detecting and generating the various analogue signals. It must be
BIAS
carefully decoupled to ensure its integrity so, apart from the decoupling capacitor shown, no other loads
should be connected. If V needs to be used to set the discriminator mid-point reference, it must be
BIAS
buffered with an external high input impedance buffer.
2013 CML Microsystems Plc
10
D/7045FI-1.x/4
CMLMICRO [ CML MICROCIRCUITS ]
