1.6
Application Notes
1.6.1 General
On power-up, it will take 80ms to initialise the internal state, this delay should be accounted for
before the DETECT output is valid.
C2
XTAL/CLOCK
1
2
3
4
8
7
6
5
X1
R5
XTALN
ENABLE
DETECT
VREF
R3
R2
CMX673P1
R1
R4
_
C3
C4
SIGIN
Phone
Line
+
Figure 3 A typical Telephone Line Circuit Application
R1 470kW
R2 470kW
R3 240kW
R4 470kW
R5
C3
C4
160kW
0.01µF 250V
0.01µF 250V
Note: 1. Resistors ±1%, Capacitors ±20% unless otherwise stated.
2. A low offset opamp is needed.
An alternative set of component values can be used:
R1 499kW
R2 499kW
R3 54.9kW
R4 499kW
R5
C3
C4
49.9kW
0.001µF 300V
0.001µF 300V
Note: 3. Resistors ±1%, Capacitors ±2% unless otherwise stated.
4. A higher value of C3 and C4 will reduce the level sensitivity tolerance at around -38dBm.
ã 2001 Consumer Microcircuits Limited
8
D/673/5
CMLMICRO [ CML MICROCIRCUITS ]
