1.3
Signal List
Package
E3
D4
P1
Signal
Description
Pin
No.
Pin
No.
Pin
No.
Name
Type
2
3
1
XTAL/CLOCK
I/P
The input to the on-chip oscillator and external
clock input. Components are on chip.
4
5
5
7
2
3
XTALN
O/P
I/P
The inverted output of the on-chip oscillator.
ENABLE
A logic ‘1’ applied to this input enables the
DETECT output. A logic ‘0’ will reset
DETECT output to a logic ‘0’.
7
8
4
5
DETECT
SIGIN
O/P
I/P
When a call progress signal is detected, this
output goes to a logic ‘1’.
10
13
Signal input. Signals to this pin should be ac
coupled. The dc bias of this pin is set
internally.
12
14
15
17
6
7
V
Power
O/P
The negative supply rail (ground).
SS
VREF
Internally generated reference voltage, held at
½V
.
DD
15
18
8
V
DD
Power
The positive supply rail. This pin should be
decoupled to V by a capacitor.
SS
1, 3, 6, 1, 2, 4,
8, 9, 6, 9,
11, 13, 10, 11,
NC
Internal Connection. Do not make any
connection to these pins.
16
12, 14,
16, 19,
20
Notes: I/P
O/P
BI
=
=
=
Input
Output
Bidirectional
ã 2001 Consumer Microcircuits Limited
4
D/673/5
CMLMICRO [ CML MICROCIRCUITS ]
