Dual SPM/Security Detector/Generator
CMX641A
1.5
General Description
1.5.1 Description of Blocks
Crystal Oscillator and Clock Dividers
These circuits derive the internal logic clocks, decode frequencies and transmit frequencies by frequency
division of a reference frequency which may be generated by the on-chip crystal oscillator or applied from
an external source.
If the on-chip oscillator is used, a 3.579545MHz crystal should be connected across the XTAL and XTALN
pins and CLOCK IN pin should be connected to CLOCK OUT. All other oscillator components are on-
chip. If an external clock source is used then it should be applied to the CLOCK IN pin and the XTAL pin
connected to V
DD
.
Input Operational Amplifiers
The input signals are input to the CMX641A via these amplifiers. In Controlled Sensitivity mode of the
Fixed Bandwidth Operating state, or when in Enhanced Features Operating state, the external
components shown in Figure 2 should be used. When used in the Fixed Sensitivity mode of the Fixed
Bandwidth Operating state, external gain setting components should be calculated using Figure 6.
In Enhanced Features Operating state, with the channels set to 12kHz/16kHz detect, the channel 2
amplifier can optionally be isolated and may be used as an independent amplifier. In this case, both
channels are internally connected to amplifier 1. The amplifiers can be connected as differential mode or
single ended, depending upon the application (see Figure 3).
SPM Tone Bandpass Filter
These are tone bandpass/audio reject filters automatically centred on the system frequency (12kHz or
16kHz) being detected. When in Controlled Sensitivity mode of the Fixed Bandwidth Operating state or
when in Enhanced Features Operating state, the level sensitivity of the device is set by adjusting the
passband gain of these filters. When in Fixed Sensitivity mode of the Fixed Bandwidth Operating state,
their gain is constant so that the internal device sensitivity is also constant.
Level Detection and Pulse Generator Circuits
The outputs from the bandpass filters are input to these circuits which perform the signal level
discrimination function for the CMX641A. Signals which fulfil the system level requirements cause a
stream of digital pulses, one per 32 cycles of input signal, to be generated. These pulses are sent to the
period measurement circuitry.
Period Measurement Logic
This digital circuit block inputs the stream of pulses from the level detection circuits and measures their
repetition rate against a predetermined maximum and minimum. Because each pulse from the level
detect circuit occur once per 32 cycles of input signal, this has the effect of averaging the input signal
period over this number of cycles. A valid SPM tone is recognised when 3 successive correctly spaced
pulses are received. If the Tone Follower output format is selected, this causes a signal to appear
immediately at the relevant channel output signifying receipt of a valid SPM signal. Depending upon the
frequency, within the legal bandwidth, received, the CMX641A should respond within 10-15ms (see
section 1.7 and Figure 5).
Tone Length Logic
This digital circuit block is used when Packet output format is selected. Its output responds when 40ms
of valid tone is received within any 48ms window, signifying receipt of a valid packet of SPM tone (see
section 1.7). Once the CMX641A has responded, within any 48ms window, 40ms of no-tone, or of tone
outside the chosen bandwidth or below the level threshold will cause the output to derespond. (See
Figure 5).
Tx Tone Generator and Shaping Filter
These are active in Enhanced Features Operating state only. They generate a low distortion sinewave
for transmission by the CMX641A as an SPM security tone. The output at the TONE OP pin is
©
2002 Consumer Microcircuits Limited
9
D/641A/5
CMLMICRO [ CML MICROCIRCUITS ]
