RALCWI Vocoder
CMX608/CMX618/CMX638
AOG register address $06 (CMX618/CMX638 only. No function on CMX608.)
7
6
0
5
0
4
0
3
2
1
0
OUTPUT GAIN SWITCH
OUTPUT GAIN
This is the analogue output gain control register. The output level should be chosen to avoid
unnecessary distortion in the output amplifier. This gain block follows the DAC, which is a sigma-
delta design with a sampling frequency of 2.4MHz and an on-chip reconstruction filter. An external
RC filter could be added across the OUTP and OUTN pins, if clock noise needs further reduction.
Bits 0 to 3
OUTPUT
GAIN
These bits control the output gain stage according to the following table:
Bit 3
Bit 2
Bit 1
Bit 0
Gain (dB)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-14 (default)
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
Bits 4 to 6
These bits are unused and should be cleared to '0'.
Bit 7
OUTPUT
GAIN
A '0' in this bit sets the earpiece gain to 0dB. A '1' in this bit sets the earpiece gain
to +6dB. A further 6dB of gain can be achieved by using both audio outputs. As
these outputs are in anti-phase, connecting the earpiece across them will provide
6dB more gain, as well as saving a dc blocking capacitor. See Figure 7.
SWITCH
2012 CML Microsystems Plc
35
D/608_18_38/10
CMLMICRO [ CML MICROCIRCUITS ]
