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CMX608Q3 参数 Datasheet PDF下载

CMX608Q3图片预览
型号: CMX608Q3
PDF下载: 下载PDF文件 查看货源
内容描述: [PCM Codec, 1-Func, LQFP-48]
分类和应用: PC电信电信集成电路
文件页数/大小: 72 页 / 2050 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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RALCWI Vocoder  
CMX608/CMX618/CMX638  
5.10. C-BUS Registers  
5.10.1.  
Command Registers  
RESET register address $01  
This register has no data associated with it. Writing to it (by the General Reset command) will  
reset the device and restore all the default settings. All registers are cleared to '0' on reset, unless  
marked otherwise. As a result, the BIAS pin is powered down and the voltage on the external  
decoupling capacitor (C14) will decay to VSS. The crystal oscillator is unaffected by writing to the  
RESET register (a "soft" reset). Instead, it is powersaved by connecting the ENABXTAL pin to VSS.  
SYNC register address $02  
This register has no data associated with it. Writing to it will synchronise the Vocoder with the host  
on the next rising edge of the CSN signal. It performs the same function as the SYNC input pin.  
Either SYNC source may be used as they are ORed together.  
SYNCCTRL register address $04  
7
0
6
0
5
0
4
0
3
2
1
0
PERIOD  
CONTROL  
Bits 0 and 1  
CONTROL  
These two bits control the Vocoder synchronisation according to the table below.  
Bit 1  
Bit 0  
Description  
0
0
1
0
1
Internal synchronisation. SYNC pin 25 is set as an input but unused. This is  
the default setting for this pin. This pin must be tied to '0' or '1' by the user.  
Internal synchronisation. SYNC pin 25 is set as an output, and a sync pulse  
is produced to allow an external device to synchronise with this one.  
Internal synchronisation. SYNC pin 25 is set as an input but unused.  
SYNC pin 25 must be tied to '0' or '1'.  
External synchronisation. SYNC pin 25 is set as an input. A sync pulse  
should be applied to this pin or this pin should be tied low and a write to the  
SYNC register ($02) will act as a sync pulse.  
0
1
1
When set for external synchronisation, the period between positive edges of the sync pulse  
applied to the SYNC pin, or the C-BUS writes to the SYNC register, should be 20ms or a multiple  
thereof. The next sync pulse after writing this register will be used as the reference. The pulse  
width must be at least 62.5µs. If the synchronisation input is provided by C-BUS, then both bits  
should be set to '1' and SYNC pin 25 should be connected to '0' (VSS).  
When the bits are set to '01', a positive-going sync pulse is output from the SYNC pin with a pulse  
width of 125µs, except in the case where bits 2 and 3 are both '0', where an 8kHz square wave is  
output from the SYNC pin instead.  
Note 1: The CODEC must be taken out of powersave by setting bit 1 in the POWERSAVE register  
($09) for sync pulses to be produced.  
Note 2: If moving between 20/40/60ms pulse settings, the 8kHz square-wave setting must be  
selected in between.  
2012 CML Microsystems Plc  
33  
D/608_18_38/10