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CMX589AD5 参数 Datasheet PDF下载

CMX589AD5图片预览
型号: CMX589AD5
PDF下载: 下载PDF文件 查看货源
内容描述: 调制解调器电路| MODEM | CMOS |专科| 24PIN |塑料\n [MODEM CIRCUIT|MODEM|CMOS|SOP|24PIN|PLASTIC ]
分类和应用: 调制解调器
文件页数/大小: 23 页 / 556 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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GMSK Modem  
CMX589A  
Data Rates  
(kbps)  
BT = 0.3  
BT = 0.5  
R1  
C1  
R1  
C1  
4
680pF  
680pF  
470pF  
390pF  
470pF  
180pF  
220pF  
180pF  
100pF  
470pF  
470pF  
220pF  
470pF  
150pF  
120pF  
150pF  
120pF  
68pF  
120kW  
100kW  
91kW  
91kW  
47kW  
100kW  
47kW  
47kW  
56kW  
120kW  
100kW  
120kW  
47kW  
91kW  
91kW  
47kW  
47kW  
51kW  
39kW  
82kW  
68kW  
62kW  
56kW  
51kW  
4.8  
8
9.6  
16  
19.2  
32  
38.4 *  
64 *  
80 *  
128 *  
144 *  
160 *  
176 *  
192 *  
68pF  
22pF  
22pF  
22pF  
22pF  
22pF  
* VDD ³ 4.5V, external clock  
Table 3: Data Rate vs. BT and Selected External Component Values  
Note: In all cases, the value of R1 should not be less than 20.0kW, and that the calculated value of C1  
includes calculated parasitic capacitance.  
2. R3, R4 and C6 form the gain components for the Rx Input signal. R3 should be chosen as required by the  
signal input level.  
3. For bit rate £ 64kbps, R4 = 100kW. For bit rate > 64kbps, R4 = 10kW.  
4. The values chosen for C2 and C3 (including stray capacitance), should be suitable for the applied VDD  
and the frequency of X1.  
As a guide: C2 = C3 = 33pF at 1.0MHz falling to 18pF at the maximum frequency.  
At 3.0V, C2 = C3 = 33pF falling to 18pF at 5.0MHz the equivalent series resistance of X1 should be less  
than 2.0KW falling to 150W at the maximum frequency. Stray capacitance on the Xtal/Clock circuit pins  
must be minimized.  
1
5. For bit rate £ 64kbps, C6 = 22pF. For bit rate > 64kbps, C6 =  
3´ bit rate´ 2p ´ 10kW  
e.g. for 128kbps, C6 = 41.1pF.  
6. C7 and C8 should both be .015mF for a data rate of 8kbps, and inversely proportional to the data rate for  
other data rates, e.g. 0.030mF at 4kbps, 1800pF at 64kbps, 680pF at 192kbps.  
7. The tolerance of C9 is not very critical because it primarily serves as a dc blocking capacitor.  
8. The CMX589A can operate correctly with the Xtal frequencies between 1.0MHz and 16.0MHz  
(VDD = 5.0V) and 1.0MHz to 5.0MHz (VDD = 3.0V). External clock frequencies up to 25.6MHz  
(VDD ³ 4.5V) are also supported (See Table 4 for examples.) For best results, a crystal oscillator design  
should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork  
crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult  
your crystal manufacturer. Operation of this device without a Xtal or Clock input may cause device  
damage.  
ã 2002 CML Microsystems Plc  
7
D/589A/4