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CMX228S1 参数 Datasheet PDF下载

CMX228S1图片预览
型号: CMX228S1
PDF下载: 下载PDF文件 查看货源
内容描述: ISDN协议引擎的D - 通道数据 [ISDN Protocol Engine with D - channel Data]
分类和应用: 电信集成电路电信电路综合业务数字网
文件页数/大小: 38 页 / 362 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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ISDN Data and Telephony Protocol Engine (inc. X.25)  
CMX228  
AC Timing Parameters (continued)  
For the following conditions unless otherwise specified:  
Xtal Frequency = 32MHz, AVDD = DVDD0 = DVDD1 = 3.0V to 5.0V, Tamb = - 40°C to +85°C.  
Read/Write operation (1/2)  
Parameter  
Address setup time  
Symbol  
Conditions  
Min.  
Max.  
Units  
VDD = +5.0V ± 10%  
(0.5 + a) T - 15  
ns  
-
tSAST  
(0.5 + a) T - 31  
(0.5 + a) T - 17  
(0.5 + a) T - 40  
0.5T - 24  
ns  
ns  
-
-
ASTB high-level width  
VDD = +5.0 V ± 10%  
VDD - +5.0 V ± 10%  
tWSTH  
tHSTLA  
ns  
ns  
-
-
Address hold time to (ASTB¯)  
0.5T - 34  
0.5T - 14  
(1 + a) T - 9  
ns  
ns  
-
-
Address hold time (to RD)  
Delay from address to RD¯  
tHRA  
tDAR  
VDD = +5.0V ±10%  
ns  
-
(1 + a) T - 15  
ns  
ns  
-
0
Address float time (to RD¯)  
-
-
tFRA  
Delay from address to data input  
VDD = +5.0V ±10%  
VDD = +5.0V ± 10%  
VDD = +5.0 V ± 10%  
(2.5 + a + n) T - 37  
ns  
tDAID  
(2.5 + a + n) T - 52  
(2 + n) T - 40  
ns  
ns  
-
-
Delay from ASTB¯ to data input  
Delay from RD¯ to data input  
tDSTID  
tDRID  
(2 + n) T - 60  
(1.5 + n) T - 50  
ns  
ns  
-
-
(1.5 + n) T - 70  
ns  
ns  
-
0.5T - 9  
Delay from ASTB¯ to RD¯  
Data hold time (to RD)  
Delay from RDto address active  
-
-
tDSTR  
tHRID  
tDRA  
0
ns  
VDD = +5.0 V ± 10%  
After program is read  
0.5T - 8  
0.5T - 12  
1.5T - 8  
-
-
-
ns  
ns  
ns  
After program is read  
VDD = +5.0 V ± 10%  
After data is read  
After data is read  
VDD = 5.0 V ± 10%  
1.5T - 12  
0.5T - 17  
(1.5 + n) T - 30  
-
-
-
ns  
ns  
Delay from RDto ASTB•  
RD low-level width  
tDRST  
tWRL  
ns  
(1.5 + n) T - 40  
0.5T - 14  
(1 + a) T - 5  
(1 + a) T - 15  
-
ns  
ns  
-
-
Address hold time (to WR)  
Delay from address to WR¯  
tHWA  
tDAW  
VDD = +5.0V ± 10%  
VDD = +5.0V ± 10%  
ns  
-
ns  
ns  
-
0.5T + 19  
Delay from ASTB¯ to data output  
tDSTOD  
0.5T + 35  
0.5T - 11  
ns  
ns  
-
-
Delay from WR¯ to data output  
Delay from ASTB¯ to WR¯  
tDWOD  
tDSTW  
0.5T - 9  
ns  
-
Where:  
T = tCYK (system clock cycle time)  
a = 1 (during address wait), otherwise, 0  
n = Number of wait states (n = 2)  
ã 1999 Consumer Microcircuits Limited  
ã 1999 Chiron Technology Limited  
36  
D/228/1  
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