Audio Scrambler and Sub-Audio Signalling Processor
CMX138A
4
Signal List
Signal
Name
TXENA
VDEC
SYSCLK
IRQN
RDATA
SCLK
CDATA
CSN
DVDD
XTAL/CLOCK
XTALN
DVSS
MOD
MICFB
MICN
MICP
Type
OP
PWR
OP
OP
TS OP
IP
IP
IP
PWR
IP
OP
PWR
OP
OP
IP
IP
Description
Digital output pin – TxENA (active low).
Internally generated 2.5V digital supply voltage. Must be decoupled to
DVSS by capacitors mounted close to the device pins. No other
connections allowed.
Synthesised digital system clock output.
C-BUS: A 'wire-ORable' output for connection to the Interrupt Request
input of the host. Pulled down to DVSS when active and is high
impedance when inactive. An external pull-up resistor is required.
C-BUS: A 3-state C-BUS serial data output to the µC. This output is high
impedance when not sending data to the µC.
C-BUS: The C-BUS serial clock input from the µC.
C-BUS: Serial data input from the µC.
C-BUS: The C-BUS chip select input from the µC - there is no internal pull-
up on this input.
The 3.3V positive supply rail for the digital on-chip circuits. This pin should
be decoupled to DVSS by capacitors mounted close to the device pins.
Input to the oscillator inverter from the Xtal circuit or external clock source.
The output of the on-chip Xtal oscillator inverter.
Digital ground.
Modulator output.
MIC input amplifier feedback.
MIC inverting input.
MIC non-inverting input.
Positive 3.3V supply rail for the analogue on-chip circuits. Levels and
thresholds within the device are proportional to this voltage. This pin
should be decoupled to AVSS by capacitors mounted close to the device
pins.
Auxiliary ADC input (inverted).
Internally generated bias voltage of about AV
DD
/2, except when the device
is in ‘Powersave’ mode when VBIAS pin will discharge to AV
SS
. Must be
decoupled to AVSS by a capacitor mounted close to the device pins. No
other connections allowed.
DISC inverting input 2.
DISC inverting input 1.
DISC input amplifier feedback.
Audio output.
Analogue ground.
Auxiliary DAC output/RAMDAC.
Digital ground.
CMX138A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
AVDD
PWR
18
AUXADC
IP
19
VBIAS
OP
20
21
22
23
24
25
26
DISCN2
DISCN1
DISCFB
AUDIO
AVSS
AUXDAC
DVSS
IP
IP
OP
OP
PWR
OP
PWR
©
2010 CML Microsystems Plc
Page 7
D/138A/2
CMLMICRO [ CML MICROCIRCUITS ]
