EP9312
Universal Platform SOC Processor
Static Memory 32-bit Read on 8-bit External Bus
Parameter
Symbol
tADs
Min
Typ
Max
Unit
tHCLK
-
AD setup to CSn assert time
CSn assert to Address transition time
Address assert time
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAD1
tHCLK × (WST1 + 1)
tHCLK × (WST1 + 1)
tHCLK × (WST1 + 2)
-
tAD2
-
-
-
tAD3
AD transition to CSn deassert time
AD hold from CSn deassert time
RDn assert time
-
tADh
tHCLK
-
-
tRDpwL
tRDd
tHCLK × (4 × WST1 + 5)
-
-
CSn to RDn delay time
-
-
-
-
-
-
-
3
1
-
tDQMd
tDAs1
tDAs2
tDAh1
tDAh2
CSn assert to DQMn assert delay time
DA setup to AD transition time
DA setup to RDn deassert time
DA hold from AD transition time
DA hold from RDn deassert time
-
15
tHCLK + 12
-
0
0
-
-
tADh
tADs
tAD1
tAD2
tAD2
tAD3
AD
CSn
WRn
RDn
tRDd
tRDd
tDQMd
DQMn
DA
1
tDAh1
tDAh1
tDAh1
tDAh2
tDAs1
tDAs1
tDAs1
tDAs2
WAIT
Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement
DS515PP7
©Copyright 2005 Cirrus Logic (All Rights Reserved)
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