EP9312
Universal Platform SOC Processor
Static Memory Single Word Read Cycle
Parameter
Symbol
tADs
Min
Typ
Max
Unit
AD setup to CSn assert time
AD hold from CSn deassert time
RDn assert time
0
-
-
-
ns
ns
ns
ns
ns
ns
ns
tADh
tHCLK
-
tRDpw
tRDd
tDQMd
tDAs
tHCLK × (WST1 + 2)
-
-
CSn to RDn delay time
-
-
-
-
-
3
1
-
CSn assert to DQMn assert delay time
DA setup to RDn deassert time
DA hold from RDn deassert time
-
tHCLK + 12
tDAh
0
-
See “Timing Conditions” on page 14 for definition of HCLK.
tADs
tADh
AD
CSn
WRn
tRDd
tRDd
RDn
tDQMd
DQMn
tDAs
tDAh
DA
WAIT
Figure 6. Static Memory Single Word Read Cycle Timing Measurement
DS515PP7
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