CS8904
Crystal LAN™ Quad Ethernet Transceiver
The MODE2, MODE1, and MODE0 pins allow
five different compatibility modes to be enabled for
the CS8904. Mode selection affects the control
signal timing and polarities of the four ports of the
CS8904. Table 1 summarizes the various modes
and the MODE2, MODE1, and MODE0 pin
settings required to select them.
4.0 FUNCTIONAL DESCRIPTION
4.1 Reset and Calibration
4.1.1 Reset Operation
Three different conditions cause the CS8904 to
reset its internal circuits:
Power-Up Reset: When power is applied, the
CS8904 maintains reset until the voltage at the
supply pins reaches approximately 2.5 V. The
CS8904 comes out of reset once Vcc is greater than
approximately 2.5 V and the crystal oscillator has
stabilized.
4.3 Controller Interface
The CS8904 provides four independent interfaces
for the digital controllers. In addition to providing
a mechanism to transfer synchronous serial data
between the CS8904 and the controller, each
interface also provides control and status
information for the port.
Power-Down Reset: If the supply voltage drops
below approximately 2.5 V, there is a chip-wide
reset. The CS8904 remains in a reset state until the
power supply returns to a level greater than
approximately 2.5 V and the crystal oscillator has
stabilized.
4.3.1 Transmit and Receive Interface
4.3.1.1 Normal Transmission
The CS8904 receives serial data from the controller
on the TxDATA pin. This data is synchronized by
the transmit clock present on the TxCLK pin. Only
one transmit clock signal is provided from the
CS8904, thus the TxCLK signal is shared by the
four interface ports. The controller causes a
transition to occur on the TxENBL pin, indicating
the start and completion of the data to be
External Reset: There is a chip-wide reset
whenever the RESET pin is held low for at least
500 ns.
4.1.2 Allowing Time for Reset
After a reset, the CS8904 resets all internal
circuitry and calibrates all on-chip analog circuitry.
The time required for the reset and calibration is transmitted. When a port is operating half duplex,
typically 36 ms. During this time, the TxCLK the transmitted data is looped back to the controller
signal is held low. When the reset and calibration during transmission on the RxDATA pin,
operations are complete, the TxCLK signal
operates as normal, oscillating at a frequency of 10
MHz.
synchronized by the receive clock present on the
RxCLK pin. This is referred to as MAU loopback
to distinguish it from the Port Loopback capability
described in Section 4.3.2 (Control and Status
Information) below.
4.2 Mode Control
The CS8904 is designed to operate with a number
of industry standard Ethernet controllers and
compatible devices. It is compatible with
controllers from Advanced Micro Devices (AMD),
Intel, Fujitsu, Seeq, National Semiconductor and
Texas Instruments.
4.3.1.2 Jabber Indication
If the serial data provided by the controller to the
CS8904 continues for greater than 100 ms, the
CS8904 will terminate the transmission of data to
the network, disable the MAU loopback of
transmitted data on the RxDATA pin, and indicate
this condition by raising the JABBER pin. The
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DS191PP2
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