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CS8900A-IQZ 参数 Datasheet PDF下载

CS8900A-IQZ图片预览
型号: CS8900A-IQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路PC局域网以太网时钟
文件页数/大小: 138 页 / 2374 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ Ethernet Controller  
base + 000Ch). If Rdy4TxNOW is set, the  
frame can be written. If clear, the host must  
wait for CS8900A buffer memory to be-  
come available. If Rdy4TxiE (Register B,  
BufCFG, Bit 8) is set, the host will be inter-  
rupted when Rdy4Tx (Register C, BufE-  
vent, Bit 8) becomes set. If the TxBidErr bit  
(Register 18, BusST, Bit 7) is set, the trans-  
mit length is not valid.  
base + 0000h) to transfer the frame from  
CS8900A memory to host memory. Pre-  
ceding the frame data are the contents of  
the RxStatus register (PacketPage base +  
0400h) and the RxLength register (Pack-  
etPage base + 0402h).  
For a more detailed description of receive, see  
Section 5.2 on page 78.  
4.10.10 Accessing Internal Registers  
3) Once the CS8900A is ready to accept the  
frame, the host executes repetitive write in-  
structions (REP OUT) to the Re-  
ceive/Transmit Data Port (I/O base +  
0000h) to transfer the entire frame from  
host memory to CS8900A memory.  
To access any of the CS8900A's internal reg-  
isters in I/O Mode, the host must first setup the  
PacketPage Pointer. It does this by writing the  
PacketPage address of the target register to  
the PacketPage Pointer Port (I/O base +  
000Ah). The contents of the target register is  
then mapped into the PacketPage Data Port  
(I/O base + 000Ch).  
For a more detailed description of transmit,  
see Section 5.6 on page 99.  
4.10.9 Basic I/O Mode Receive  
If the host needs to access a sequential block  
of registers, the MSB of the PacketPage ad-  
I/O Mode receive operations occur in the fol-  
lowing order (In this example, interrupts are dress of the first word to be accessed should  
enabled to signal the presence of a valid re-  
ceive frame):  
be set to "1". The PacketPage Pointer will then  
move to the next word location automatically,  
eliminating the need to setup the PacketPage  
Pointer between successive accesses (see  
Figure 18).  
1) A frame is received by the CS8900A, trig-  
gering an enabled interrupt.  
2) The host reads the Interrupt Status Queue  
Port (I/O base + 0008h) and is informed of  
the receive frame.  
4.10.11 Polling the CS8900A in I/O Mode  
If interrupts are not used, the host can poll the  
CS8900A to check if receive frames are  
present and if memory space is available for  
transmit.  
3) The host reads the frame data by execut-  
ing repetitive read instructions (REP IN)  
from the Receive/Transmit Data Port (I/O  
CIRRUS LOGIC PRODUCT DATASHEET  
DS271F4  
77