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CS8900A-IQZ 参数 Datasheet PDF下载

CS8900A-IQZ图片预览
型号: CS8900A-IQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路PC局域网以太网时钟
文件页数/大小: 138 页 / 2374 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ Ethernet Controller  
4.7 Receive and Transmit Frame Locations CFG, bit BufferCRC). If CRC has not been se-  
lected, then the length does not include the  
CRC, and the CRC is not present in the re-  
ceive buffer.  
The Receive and Transmit Frame PacketPage  
locations are used to transfer Ethernet frames  
to and from the host. The host sequentially  
writes to and reads from these locations, and  
internal buffer memory is dynamically allocat-  
ed between transmit and receive as needed.  
One receive frame and one transmit frame are  
accessible at a time.  
After the RxLength has been read, the receive  
frame can be read. When some portion of the  
frame is read, the entire frame should be read  
before reading the RxEvent register either di-  
rectly or through the ISQ register. Reading the  
RxEvent register signals to the CS8900A that  
the host is finished with the current frame, and  
wants to start processing the next frame. In  
this case, the current frame will no longer be  
accessible to the host. The current frame will  
also become inaccessible if a Skip command  
is issued, or if the entire frame has been read.  
See Section 5.2 on page 78.  
4.7.1 Receive PacketPage Locations  
In IO mode, the receive status/length/frame lo-  
cations are read through repetitive reads from  
one IO port at the IO base address. See  
Section 4.10 on page 75.  
In memory mode, the receive sta-  
tus/length/frame locations are read using  
memory reads of a block of memory starting at  
memory base address + 0400h. Typically the  
memory locations are read sequentially using  
repetitive Move instructions (REP MOVS).  
See Section 4.9 on page 73.  
4.7.2 Transmit Locations  
The host can write frames into the CS8900A  
buffer using Memory writes using REP MOVS  
to the TxFrame location. See Section 5.6 on  
page 99.  
Random access is not needed. However, the  
first 118 bytes of the receive frame can be ac-  
cessed randomly if word reads, on even word  
boundaries, are used. Beyond 118 bytes, the  
memory reads must be sequential. Byte reads,  
or reads on odd-word boundaries, can be per-  
formed only in sequential read mode. See  
Section 4.8 on page 72.  
4.8 Eight and Sixteen Bit Transfers  
A data transfer to or from the CS8900A can be  
done in either I/O or Memory space, and can  
be either 16 bits wide (word transfers) or 8 bits  
wide (byte transfers). Because the CS8900A’s  
internal architecture is based on a 16-bit data  
bus, word transfers are the most efficient.  
The RxStatus word reports the status of the  
current received frame. RxEvent register 4  
(PacketPage base + 0124h) has the same  
contents as the RxStatus register, except Rx-  
Event is cleared when RxEvent is read.  
To transfer transmit frames to the CS8900A  
and receive frames from the CS8900A, the  
host may mix word and byte transfers, provid-  
ed it follows three rules:  
1) The primary method used to access  
The RxLength (receive length) word is the  
length, in bytes, of the data to be transferred to  
the host across the ISA bus. The register de-  
scribes the length from the start of Destination  
Address to the end of CRC, assuming that  
CRC has been selected (via Register 3 Rx-  
CS8900A  
memory is word access.  
2) Word accesses to the CS8900A’s internal  
memory are kept on even-byte boundaries.  
3) When switching from byte accesses to  
word accesses, a byte access to an even  
CIRRUS LOGIC PRODUCT DATASHEET  
72  
DS271F4  
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