CS8900A
Crystal LAN™ ISA Ethernet Controller
4.4.15 Register 10: Transmit Collision Counter
(TxCOL, Read-only, Address: PacketPage base + 0132h)
7
6
5
4
3
2
1
9
0
8
ColCount
010010
F
E
D
C
B
A
ColCount
The TxCOL counter (Bits 6 through F) is incremented whenever the 10BASE-T Receive Pair (RXD+ / RXD-) or AUI
Collision Pair (CI+ / CI-) becomes active while a packet is being transmitted. If the TxColOvfiE bit (Register B,
BufCFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides the
host with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over (by inter-
rupting at 200h, the host has an additional 512 counts before TxCOL actually overflows). The TxCOL counter is
cleared when read.
010010
These bits provide an internal address used by the CS8900A to identify this as the Transmit
Collision Counter. When reading this register, these bits will be 010010, where the LSB corre-
sponds to Bit 0.
ColCount
The upper ten bits contain the number of collisions.
Reset value is: 0000 0000 0001 0010
CIRRUS LOGIC PRODUCT DATA SHEET
62
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
