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CS8900A-IQ 参数 Datasheet PDF下载

CS8900A-IQ图片预览
型号: CS8900A-IQ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
EEDataIn - EEPROM Data In, Input Internal Weak Pullup PIN 6.  
Serial input used to receive data from the EEPROM. Connects to the DO pin on the EEPROM.  
EEDataIn is also used to sense the presence of the EEPROM.  
ELCS - External Logic Chip Select, Internal Weak Pullup PIN 2.  
Bi-directional signal used to configure external Latchable Address (LA) decode logic. If  
external LA decode logic is not needed, ELCS should be tied low.  
EEDataOut - EEPROM Data Out,PIN 5.  
Serial output used to send data to the EEPROM. Connects to the DI pin on the EEPROM.  
When TEST is low, this pin becomes the output for the Boundary Scan Test.  
CSOUT - Chip Select for External Boot PROM, PIN 17.  
Active-low output used to select an external Boot PROM when the CS8900A decodes a valid  
Boot PROM memory address.  
10BASE-T Interface  
TXD+/TXD- - 10BASE-T Transmit, Differential Output Pair PINS 87 and 88.  
Differential output pair drives 10 Mb/s Manchester-encoded data to the 10BASE-T transmit  
pair.  
RXD+/RXD- - 10BASE-T Receive, Differential Input Pair PINS 91 and 92.  
Differential input pair receives 10 Mb/s Manchester-encoded data from the 10BASE-T receive  
pair.  
Attachment Unit Interface (AUI)  
DO+/DO- - AUI Data Out, Differential Output Pair PINS 83 and 84.  
Differential output pair drives 10 Mb/s Manchester-encoded data to the AUI transmit pair.  
DI+/DI- - AUI Data In, Differential Input Pair PINS 79 and 80.  
Differential input pair receives 10 Mb/s Manchester-encoded data from the AUI receive pair.  
CI+/CI- - AUI Collision In, Differential Input Pair PINS 81 and 82.  
Differential input pair connects to the AUI collision pair. A collision is indicated by the  
presence of a 10 MHz ± 15% signal with duty cycle no worse than 60/40.  
General Pins  
XTAL[1:2] - Crystal, Input/Output PINS 97 and 98.  
A 20 MHz crystal should be connected across these pins. If a crystal is not used, a 20 MHz  
signal should be connected to XTAL1 and XTAL2 should be left open. (See Section 7.3 on  
page 111 and Section 7.7 on page 121.)  
CIRRUS LOGIC PRODUCT DATA SHEET  
DS271PP3  
15  
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