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CS8900A-IQ 参数 Datasheet PDF下载

CS8900A-IQ图片预览
型号: CS8900A-IQ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
ISA Bus Interface  
SA[0:19] - System Address Bus, Input PINS 37-48, 50-54, 58-60.  
Lower 20 bits of the 24-bit System Address Bus used to decode accesses to CS8900A I/O and  
Memory space, and attached Boot PROM. SA0-SA15 are used for I/O Read and Write  
operations. SA0-SA19 are used in conjunction with external decode logic for Memory Read  
and Write operations.  
SD[0:15] - System Data Bus, Bi-Directional with 3-State Output PINS 65-68, 71-74, 27-24, 21-18.  
Bi-directional 16-bit System Data Bus used to transfer data between the CS8900A and the host.  
RESET - Reset, Input PIN 75.  
Active-high asynchronous input used to reset the CS8900A. Must be stable for at least 400 ns  
before the CS8900A recognizes the signal as a valid reset.  
AEN - Address Enable, Input PIN 63.  
When TEST is high, this active-high input indicates to the CS8900A that the system DMA  
controller has control of the ISA bus. When AEN is high, the CS8900A will not perform slave  
I/O space operations. When TEST is low, this pin becomes the shift clock input for the  
Boundary Scan Test. AEN should be inactive when performing an IO or memory access and it  
should be active during a DMA cycle.  
MEMR - Memory Read, Input PIN 29.  
Active-low input indicates that the host is executing a Memory Read operation.  
MEMW - Memory Write, Input PIN 28.  
Active-low input indicates that the host is executing a Memory Write operation.  
MEMCS16 - Memory Chip Select 16-bit, Open Drain Output PIN 34.  
Open-drain, active-low output generated by the CS8900A when it recognizes an address on the  
ISA bus that corresponds to its assigned Memory space (CS8900A must be in Memory Mode  
with the MemoryE bit (Register 17, BusCTL, Bit A) set for MEMCS16 to go active). 3-Stated  
when not active.  
REFRESH - Refresh, Input PIN 49.  
Active-low input indicates to the CS8900A that a DRAM refresh cycle is in progress. When  
REFRESH is low, MEMR, MEMW, IOR, IOW, DMACK0, DMACK1, and DMACK2 are  
ignored.  
IOR - I/O Read, Input PIN 61.  
When IOR is low and a valid address is detected, the CS8900A outputs the contents of the  
selected 16-bit I/O register onto the System Data Bus. IOR is ignored if REFRESH is low.  
IOW - I/O Write, Input PIN 62.  
When IOW is low and a valid address is detected, the CS8900A writes the data on the System  
Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low.  
CIRRUS LOGIC PRODUCT DATA SHEET  
DS271PP3  
13  
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