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CS5513-BS 参数 Datasheet PDF下载

CS5513-BS图片预览
型号: CS5513-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 16位和20位, 8引脚Σ-Δ型ADC [16-bit and 20-bit, 8-pin Sigma-Delta ADC]
分类和应用:
文件页数/大小: 24 页 / 408 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5510/11/12/13  
priate time during the third conversion cycle to en-  
sure the maximum possible throughput.  
will be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for  
the CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for  
the CS5512/13. The gain error (GE) is equal to: (Cr  
- ZP)/Ci. To correct for both offset and gain error in  
subsequent conversions, subtract the offset error,  
and then divide by the gain error.  
2.6 Digital Off-chip System  
Calibration  
The CS5510/11/12/13 exhibit excellent linearity  
with low offset and gain drift, without the need for  
calibration. If precision voltage measurements are  
required by the system, however, software-based  
offset and gain calibration can be performed by the  
system.  
2.7 Power Consumption, Sleep and  
Reset  
The CS5510/11/12/13 accommodates two power  
modes: normal and sleep. The normal mode is the  
default mode and is entered after power is estab-  
lished to the ADC. In normal mode, the ADCs typ-  
ically consumes 2.5 mW. Sleep is entered when  
the user leaves SCLK high for at least 200 µs. The  
ADCs are guaranteed to be in sleep after SCLK is  
high (logic 1) for 2 ms. The sleep mode reduces  
the consumed power to less than 10 µW when CS  
is high (logic 1). If CS is low (logic 0) at this time,  
the SDO drive logic will still be active, and the con-  
sumed sleep power will be greater. To exit sleep  
and return to normal mode, the user must return  
SCLK low for at least 10 µs. After a sleep is exited,  
the ADCs reset all their internal logic, including  
their digital filters, and begin performing conver-  
sions. Since the filters are reset, the first three con-  
version after returning to normal mode will not be  
fully settled.  
To perform a software offset calibration, the “zero-  
point” of the system should be established by ap-  
plying an input to the system equal to zero. Then,  
the user can obtain a conversion and store it in  
memory as the system’s zero point (ZP). This num-  
ber can then be used as the zero point for any sub-  
sequent conversion words. In the 20-bit devices  
(CS5512 and CS5513), multiple conversions can  
be averaged to arrive at a more accurate offset val-  
ue. In the 16-bit devices (CS5510 and CS5511),  
averaging may not be meaningful, because the  
noise will be below the size of one LSB when using  
nominal voltages for VREF (2.5 V).  
A software gain calibration can be performed by  
bringing the system to a known calibration Voltage  
value (Vcal) and acquiring a conversion (note that  
Vcal should be low enough to compensate for the  
possible gain error of the ADC). Multiple conver-  
sions can be averaged at this point to improve the  
accuracy of the calibration. The code obtained  
from this conversion is the real value (Cr) of the  
calibration Voltage input, and will differ from the  
ideal value. The ideal value for this conversion (Ci)  
2.8 PCB Layout  
The CS5510/11/12/13 should be placed entirely  
over the analog ground. Place the analog-digital  
plane split immediately adjacent to the digital pins  
of the chip.  
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DS337F3