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CS5513-BS 参数 Datasheet PDF下载

CS5513-BS图片预览
型号: CS5513-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 16位和20位, 8引脚Σ-Δ型ADC [16-bit and 20-bit, 8-pin Sigma-Delta ADC]
分类和应用:
文件页数/大小: 24 页 / 408 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5510/11/12/13  
Bipolar Input Voltage  
Two's Complement (20-Bit) Two's Complement (16-Bit)  
>(VFS-1.5 LSB)  
7FFFF  
7FFF  
7FFFF  
-----  
7FFFE  
7FFF  
-----  
7FFE  
VFS-1.5 LSB  
-0.5 LSB  
00000  
-----  
0000  
-----  
FFFFF  
FFFF  
80001  
-----  
8001  
-----  
-VFS+0.5 LSB  
80000  
8000  
Note: VFS in the table equals the voltage between AIN+ and AIN-. See text about error flags  
under overrange conditions.  
Table 3. CS5510/11/12/13 Output Coding.  
cessively overranged. If the OD bit is set, the con-  
version data bits can be completely erroneous. The  
OD flag bit will be cleared to logic 0 four output  
words after the modulator becomes stable again.  
The OD flag can occur independent of OF with a  
spike on the input. Both flag bits should be tested  
if any overrange condition occurs.  
(CLK represents SCLK for the CS5510/12 and the  
internal oscillator for the CS5511/13). The filters  
are optimized to yield better than 80 dB rejection  
between 47 Hz to 63 Hz (i.e. 80 dB minimum rejec-  
tion for both 50 Hz and 60 Hz) when the master  
clock is 32.768 kHz. The filter has a response as  
shown in Figure 20. Table 4 shows the filter re-  
sponse for frequencies from 38 Hz to 71 Hz. Note  
that the response of the CS5511/13 will be similar,  
but the frequencies scale with the on-chip oscilla-  
tor’s frequency, which can be from 32 kHz to  
96 kHz (i.e. conversion rates can vary between  
53 Sps to 159 Sps). Further note that after initial  
power up, or after returning from sleep mode, the  
filter requires four conversion cycles to produce a  
Table 3 illustrates the output coding for the  
CS5510/11/12/13. Conversions are output as  
two's complement values representing bipolar in-  
put signals.  
2.5.4 Digital Filter  
The CS5510/11/12/13 have a modified Sinc4 digi-  
tal filter that provides CLK/612 Hz conversion rates  
D23  
0
D11  
11  
D22  
OF  
D10  
10  
D21  
OD  
D9  
9
D20  
0
D8  
8
D19  
MSB  
D7  
D18  
18  
D6  
6
D17  
17  
D5  
5
D16  
16  
D4  
4
D15  
15  
D3  
3
D14  
14  
D2  
2
D13  
13  
D1  
1
D12  
12  
D0  
7
LSB  
Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits).  
D23  
0
D11  
11  
D22  
OF  
D10  
10  
D21  
OD  
D9  
9
D20  
0
D8  
8
D19  
0
D7  
7
D18  
0
D6  
6
D17  
0
D5  
5
D16  
0
D4  
4
D15  
MSB  
D3  
D14  
14  
D2  
2
D13  
13  
D1  
1
D12  
12  
D0  
3
LSB  
Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits).  
18  
DS337F3