CS5460A
b) The common-mode rejection performance of the
CS5460A is sufficient within the frequency range
over which the CS5460A performs A/D conver-
sions. Addition of such common-mode caps can
actually often degrade the common-mode rejec-
tion performance of the entire voltage/current input
networks. Therefore, choosing relatively small val-
ues for (CV+, CV-, CI+, CI-) will provide necessary
common-mode rejection at the much higher fre-
quencies, and will allow the CS5460A to realize its
CMRR performance in the frequency-range of in-
terest.
pressed in rads/s). Subtracting these two
time-constants shows that after the voltage/current
signals pass through their respective anti-aliasing
filters, the sensed voltage signal will be delayed
~0.329 µs more than the current signal. If metering
a 60 Hz power system, this implies that the input
voltage-sense
signal
will
be
delayed
~0.007 degrees more than the delay imposed on
the input current-sense signal. Note that when the
PC[6:0] bits are set to their default setting of
“0000000”, the internal filtering stages of the
CS5460A will impose an additional delay on the
fundamental frequency component of the 60Hz
voltage signal of 0.0215 degrees, with respect to
the current signal. The total difference between the
delay on the voltage-sense fundamental and the
current-sense fundamental will therefore be
~0.286 degrees. But if the phase compensation
bits are set to 1111111, the CS5460A will delay the
voltage channel signal by an additional -0.04 de-
grees, which is equivalent to shifting the voltage
signal forward by 0.04 degrees. The total phase
shift on the voltage-sense signal (with respect to
the fundamental frequency) would then be
~0.011 degrees ahead of the current-sense signal,
which would therefore provide more close-
ly-matched delay values between the volt-
age-sense and current-sense signals. Adjustment
of the PC[6:0] bits therefore can provide an effec-
tive way to more closely match the delays of the
voltage/current sensor signals, allowing for more
commonly available R and C component values to
be used in both of these filters.
[Note that this discussion does not include correc-
tion of phase-shifts caused by the voltage-sense
transformer and current-sense transformer, al-
though these phase-shifts should definitely be con-
sidered in a real-life practical meter design.] On the
current channel, using commonly available values
for the components, RI+ and RI- can be set to
470 Ω. Then a value of CIdiff = 18 nF and a value of
0.22 nF for CI- and CI- will yield a -3 dB cutoff fre-
quency of 15341 Hz for the current channel. For
the voltage channel, if RI+ and RI- are also set to
470 Ω, CVdiff = 18 nF, and CV- = CV- = 0.22 nF
(same as current channel), the -3 dB cutoff fre-
quency of the voltage channel’s input filter will be
14870 Hz. The difference in the two cutoff frequen-
cies is due to the difference in the input impedance
between the voltage/current channels.
If there is concern about the effect that the differ-
ence in these two cutoff frequencies (and therefore
the mis-match between the time-constants of the
overall voltage/current input networks) would have
on the accuracy of the power/energy registration, a
non-standard resistor value for RV+ = RV- of (for ex-
ample) 455 Ω can be used. This would shift the
(differential) -3 dB cutoff frequency of the voltage
channel’s input filter (at the voltage channel inputs)
to ~15370 Hz, which would cause the first-order
time-constants of the voltage/current channel input
filters to be closer in value.
As a final note, tolerances of the R and C compo-
nents that are used to build the two R-C filters
should also be taken into consideration. A com-
mon tolerance of 0.1% can vary the delay by as
much as much as ~ 2.07 µs, which means that the
difference between the delays of the voltage-sense
and current-sense signals that is caused by these
filters could vary by as much as ~ 4.1 µs, which is
equivalent to a phase shift of ~ 0.089 degrees (at
60 Hz). This in turn implies that our decision to ad-
just the PC[6:0] bits (to shift the voltage signal for-
ward by 0.04 degrees) could actually cause the
voltage signal to be shifted by as much as
~0.100 degrees ahead of the current signal.
Thus, adjustment of the PC[6:0] bits to more close-
ly match the two time-constants/delays may only
be useful if a precise calibration operation can be
Agreement between the voltage/current channel
time-constants can also be obtained by adjusting
the phase compensation bits, instead of using less
commonly-available resistor/capacitor values
(such as RI+ = RI- = 455 Ω). If the values of RI+ and
RI- are again 470 Ω, the first-order time-constants
of the two R-C filters are estimated by taking the re-
ciprocal of the -3 dB cutoff frequencies (when ex-
36
CIRRUS [ CIRRUS LOGIC ]
