CS5361
3.0 TYPICAL CONNECTION DIAGRAM
+5 Vto 3.3 V
+
+5Vto2.5 V
+
µ
1 F
µF
µ
1 F
0.01
µ
0.01 F
*
+5V
µF
0.01
+
µ
µ
Ω
5.1
1 F
0.01 F
FILT+
D
V
L
V
VA
VL
+
µ
µ
0.01 F
**47 F
10 k
REFGND
µ
µ
1 F
0.01 F
OVFL
RST
I2S/LJ
M/S
HPF
M0
+
VQ
Power Down
and Mode
Settings
AINL+
Analog
Input
Buffer
CS5361
A/D CONVERTER
M1
MDIV
(Figure 24)
AINL-
Audio Data
Processor
SDOUT
LRCK
AINR+
AINR-
Analog
Input
Buffer
Timing Logic
and Clock
SCLK
MCLK
(Figure 24)
* Resistor may only
be used if VD is
derived from VA. If
used, do not drive any
other logic from VD.
GND
GND
Figure 22. Typical Connection Diagram
DS467F2
15