CS49300 Family DSP
name corresponding to their particular use.
filter circuit will be directly coupled into the PLL,
Sometimes GPIO[11:0], or some subset thereof, is which could affect performance.
used when referring to the pins in a general sense.
Reference Designator
Value
2.2uF
220pF
10nF
C1
3.2. Termination Requirements
C2
The CS493XX incorporates open drain pins which
must be pulled high for proper operation. INTREQ
C3
R1
200k Ohm
(pin 20) is always an open drain pin which requires
2
Table 1. PLL Filter Component Values
a pull-up for proper operation. When in the I C
serial communication mode, the SCDIO signal (pin
19) is open drain and thus requires a pull-up for
proper operation.
4. POWER
The CS493XX requires a 2.5V digital power
supply for the digital logic within the DSP and a
2.5V analog power supply for the internal PLL.
There are three digital power pins, VD1, VD2 and
VD3, along with three digital grounds, DGND1,
DGND2 and DGND3. There is one analog power
pin, VA and one analog ground, AGND. The DSP
will perform at its best when noise has been
eliminated from the power supply. The
recommendations given below for decoupling and
power conditioning of the CS493XX will help to
ensure reliable performance.
Due to the internal, multiplexed design of the pins,
certain signals may or may not require termination
depending on the mode being used. If a parallel
host communication mode is not being used,
GPIO[11:0] must be terminated or driven as these
pins will come up as high impedance inputs and
will be prone to oscillation if they are left floating.
The specific termination requirements may vary
since the state of some of the GPIO pins will
determine the communication mode at the rising
edge of reset (please see Section 6, “Control” on
page 32 for more information). For the explicit
termination requirements of each communication
mode please see the typical connection diagrams.
4.1. Decoupling
It is good practice to decouple noise from the
power supply by placing capacitors directly
between the power and ground of the CS493XX.
Each pair of power pins (VD1/DGND,
VD2/DGND, VD3/DGND, VA/AGND) should
have its own decoupling capacitors. The
recommended procedure is to place both a 0.1uF
and a 1uF capacitor as close as physically possible
to each power pin. The 0.1uF capacitor should be
closest to the part (typically 5mm or closer).
Generally a 4.7k Ohm resistor is recommended for
open drain pins. The communication mode setting
pins (please see Section 6, “Control” on page 32 for
more information) should also be terminated with a
4.7k resistor. A 10k Ohm resistor is sufficient for
the GPIO pins and unused inputs.
3.3. Phase Locked Loop Filter
The internal phase locked loop (PLL) of the
CS493XX requires an external filter for successful
operation. The topology of this filter is shown in
the typical connection diagrams. The component
values are shown below. Care should be taken
when laying out the filter circuitry to minimize
trace lengths and to avoid any close routing of high
frequency signals. Any noise coupled on to the
4.2. Analog Power Conditioning
In order to obtain the best performance from the
CS493XX’s internal PLL, the analog power supply
(VA) must be as clean as possible. A ferrite bead
should be used to filter the 2.5V power supply for
the analog portion of the CS493XX. This power
DS339PP4
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CIRRUS [ CIRRUS LOGIC ]
