CS4923/4/5/6/7/8/9
The CDI can be configured to support I2S, left
justified and right justified formats. The CDI can
also be programmed for slave clocks, where
LRCLKN2 and SCLKN2 are inputs, or master
clocks, where LRCLKN2 and SCLKN2 are
outputs. In order for clocks to be mastered, the
internal PLL must be used.
7.2 Digital Audio Input Port
The digital audio input port, or DAI, is used for
both compressed and PCM digital audio data input.
In addition this port supports a special clocking
mode in which a clock can be input to directly drive
the internal 33 bit counter. Table 10 shows the pin
names, mnemonics and pin numbers associated
with the DAI.
In addition the CDI can be configured for bursty
compressed data input. Bursty audio delivery is a
special format in which only clock (CMPCLK) and
data (CMPDAT) are used to deliver compressed
data to the CS4923/4/5/6/7/8/9 (i.e. no frame clock
or LRCLK). A third line, CMPREQ, is used to
request more data from the host. It is an indicator
that the CS492X internal FIFO is low on data and
can accept another burst. Typically this mode is
used for compressed data delivery where
asynchronous data transfer occurs in the system,
i.e. in a system such as a set-top box or HDTV.
PCM data can not be presented in this mode since
data is interpreted as a continuous stream with no
word boundaries.
Pin Name
SDATAN1
SCLKN1
Pin Description
Serial Data In
Serial Bit Clock
Frame Clock
Pin Number
22
25
26
LRCLKN1
Table 10. Digital Audio Input Port
The DAI can be programmed to support I2S, left
justified and right justified data input. In addition
the DAI can be programmed for slave clocks,
where LRCLKN1 and SCLKN1 are inputs, or
master clocks, where LRCLKN1 and SCLKN1 are
outputs. In order for clocks to be master, the
internal PLL must be used.
STCCLK2 can also be programmed to drive the
internal 33 bit counter. This counter would
typically be driven by a 90kHz clock. The internal
counter is used by certain application code for
audio/video synchronization purposes.
7.4 Parallel Digital Audio Data Input
If using the Intel or Motorola Parallel host interface
mode, the system designer can also choose to
deliver data through the byte wide parallel port.
The compressed data input register receives bytes
of data when the host interface writes to address
11b (A1 and A0 are both high). The host interface
port also utilizes the CMPREQ pin and the MFB
and MFC flags in the CONTROL register, which
are configurable to supply a data request flag at
different input buffer thresholds. CMPREQ acts as
an almost full flag. The CS4923/4/5/6/7/8/9 can
safely receive different size blocks of data
depending on the level of the input buffer
threshold. The threshold level is programmable and
the default level may differ between applications.
This mode reduces the polling burden associated
with hand-feeding the compressed data.
7.3 Compressed Data Input Port
The compressed data input port, or CDI, can be
used for both compressed and PCM data input.
Table 11 shows the mnemonic, pin name and pin
number of the pins associated with the CDI port on
the CS4923/4/5/6/7/8/9.
Pin Name
SDATAN2
CMPDATA
SCLKN2
Pin Description
Serial Data In
Compressed Data In
Pin Number
27
Serial Bit Clock
28
29
CMPCLK
LRCLKN2
CMPREQ
Frame Clock
Data Request Out
Table 11. Compressed Data Input Port
46
DS262F2
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