CS4923/4/5/6/7/8/9
presented most significant bit first on the first
SCLK after an LRCLK transition and is valid on
the rising edge of SCLK. For the left justified
format, the left subframe is presented when
LRCLK is high and the right subframe is presented
when LRCLK is low. The left justified format can
also be programmed for data to be valid on the
falling edge of SCLK. SCLK is required to run at a
frequency of 48Fs or greater on the input ports.
7. DIGITAL INPUT & OUTPUT
The CS4923/4/5/6/7/8/9 supports a wide variety of
data input and output mechanisms through various
input and output ports. Hardware availability is
entirely dependent on whether the software
application code being used supports the required
mode. This data sheet presents most of the modes
available with the CS4923/4/5/6/7/8/9 hardware.
This does not mean that all of the modes are
available with any particular piece of application
code. Both the CS4923/4/5/6/7/8/9 Hardware
User’s Guide and the application code user’s guide
for the particular code being used should be
referenced to determine if a particular mode is
supported.
Right Justified: Figure 26 shows the right justified
format. The right justified format is similar to the
left justified format except the least significant bit
is right justified to be valid on the last transition of
SCLK before an LRCLK transition. Data is still
presented most significant bit first. For the right
justified format, the left subframe is presented
when LRCLK is high and the right subframe is
presented when LRCLK is low. The right justified
format can also be programmed for data being valid
on the falling edge of SCLK. SCLK is required to
run at a frequency of 48Fs or greater on the input
ports.
7.1 Digital Audio Formats
This subsection will describe some common audio
formats that the CS4923/4/5/6/7/8/9 supports. It
should be noted that the input ports use up to 24-bit
PCM resolution and 16-bit compressed data word
lengths. The output port of the CS492X provides
up to 20-bit PCM resolution.
Multi-Channel: Figure 27 shows the multi-
channel format. In this format up to 6 channels of
audio are presented on one data line with 20 bits per
channel. Channels 0, 2, and 4 are presented while
the LR-CLK is high and channels 1, 3, 5 are
presented while the LRCLK is low. Data is valid on
the rising edge of SCLK and is presented most
significant bit first.
I2S: Figure 24 shows the I2S format. For I2S, data is
presented most significant bit first, one SCLK
delay after the transition of LRCLK and is valid on
the rising edge of SCLK. For the I2S format, the left
subframe is presented when LRCLK is low and the
right subframe is presented when LRCLK is high.
SCLK is required to run at a frequency of 48Fs or
greater on the input ports.
Because each of the ports is fully configurable,
there may be modes that can be supported which
are not presented.
Left Justified: Figure 25 shows the left justified
format with a rising edge SCCLK. Data is
44
DS262F2
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