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CS4926-CL 参数 Datasheet PDF下载

CS4926-CL图片预览
型号: CS4926-CL
PDF下载: 下载PDF文件 查看货源
内容描述: 多声道数字音频解码器 [Multi-Channel Digital Audio Decoders]
分类和应用: 解码器
文件页数/大小: 56 页 / 648 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4923/4/5/6/7/8/9  
6.4 I2C Serial Host Interface .................................................................................................. 39  
6.4.1  
6.4.2  
I2C Write ......................................................................................................... 39  
I2C Read ......................................................................................................... 39  
6.5 External Memory .............................................................................................................. 41  
6.5.1 External Memory and Autoboot ...................................................................... 43  
7. DIGITAL INPUT & OUTPUT .................................................................................................. 44  
7.1 Digital Audio Formats ....................................................................................................... 44  
7.2 Digital Audio Input Port .................................................................................................... 46  
7.3 Compressed Data Input Port ........................................................................................... 46  
7.4 Parallel Digital Audio Data Input ...................................................................................... 46  
7.5 Digital Audio Output Port ................................................................................................. 47  
7.5.1  
IEC60958 Output ............................................................................................ 48  
8. PIN DESCRIPTIONS .............................................................................................................. 49  
9. PACKAGE DIMENSIONS ...................................................................................................... 54  
LIST OF FIGURES  
Figure 1. RESET Timing.................................................................................................................. 5  
Figure 2. Serial Compressed Data Timing ....................................................................................... 6  
Figure 3. CLKIN with CLKSEL = VSS = PLL Enable........................................................................ 7  
Figure 4. CLKIN with CLKSEL = VD = PLL Bypass ......................................................................... 7  
Figure 5. Intel Parallel Host Mode Read Cycle................................................................................. 9  
Figure 6. Intel Parallel Host Mode Write Cycle................................................................................. 9  
Figure 7. Motorola Parallel Host Mode Read Cycle ....................................................................... 11  
Figure 8. Motorola Parallel Host Mode Write Cycle........................................................................ 11  
Figure 9. SPI Control Port Timing................................................................................................... 13  
Figure 10. I2C Control Port Timing ................................................................................................. 15  
Figure 11. Digital Audio Input, Data and Clock Timing................................................................... 17  
Figure 12. Digital Audio Output, Data and Clock Timing................................................................ 19  
Figure 13. I2C Control..................................................................................................................... 25  
Figure 14. I2C Control with External Memory................................................................................. 26  
Figure 15. SPI Control.................................................................................................................... 27  
Figure 16. SPI Control with External Memory ................................................................................ 28  
Figure 17. Intel Parallel Control Mode............................................................................................ 29  
Figure 18. Motorola Parallel Control Mode..................................................................................... 30  
Figure 19. SPI Timing..................................................................................................................... 38  
Figure 20. I2C Timing ..................................................................................................................... 40  
Figure 21. External Memory Interface ............................................................................................ 42  
Figure 22. Run-Time Memory Access............................................................................................ 42  
Figure 23. Autoboot Timing Diagram.............................................................................................. 43  
Figure 24. I2S Format..................................................................................................................... 45  
Figure 25. Left Justified Format...................................................................................................... 45  
Figure 26. Right Justified................................................................................................................ 45  
Figure 27. Multi-Channel Format (M == 20) ................................................................................... 45  
LIST OF TABLES  
Table 1. Silicon Revisions .............................................................................................................. 20  
Table 2. Host Modes ...................................................................................................................... 33  
Table 3. Host Memory Map ............................................................................................................ 34  
Table 4. Intel Parallel Host Mode Pin Assignments........................................................................ 34  
Table 5. Parallel Input/Output Registers......................................................................................... 35  
Table 6. Motorola Parallel Host Mode Pin Assignments ................................................................ 36  
Table 7. SPI Serial Mode Pin Assignments.................................................................................... 36  
Table 8. I2C Serial Mode Pin Assignments .................................................................................... 39  
Table 9. Memory Interface Pins...................................................................................................... 41  
Table 10. Digital Audio Input Port................................................................................................... 46  
Table 11. Compressed Data Input Port.......................................................................................... 46  
Table 12. Digital Audio Output Port................................................................................................ 47  
Table 13. MCLK/SCLK Master Mode Ratios.................................................................................. 47  
DS262F2  
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