CS4923/4/5/6/7/8/9
Some pins are designed to operate in one mode at
power up, and serve a different purpose when the
DSP is running. Other pins have functionality
which can be controlled by the application running
on the DSP. In order to better explain the behavior
of the part, the pins which are multiplexed have
been given multiple names. Each name is specific
to the pin’s operation in a particular mode.
3. TYPICAL CONNECTION
DIAGRAMS
Six typical connection diagrams have been
presented to illustrate using the device with the
different communication modes available. They
are as follows:
2
Figure 13: I C Control
2
Figure 14: I C Control with External Memory
An example of this would be the use of pin 20 in
one of the serial control modes. During the boot
period of the CS492X, pin 20 is called ABOOT.
ABOOT is sampled on the rising edge of RESET.
If ABOOT is high the host must download code to
the DSP. If ABOOT is low when sampled, the
CS492X goes into autoboot mode and loads itself
with code by generating addresses and reading data
on EMAD[7:0]. When the device has been loaded
Figure 15: SPI Control
Figure 16: SPI Control with External Memory
Figure 17: Intel Parallel Control Mode
Figure 18: Motorola Parallel Control Mode
The following should be noted when viewing the
typical connection diagrams:
The pins are grouped functionally in each of the
typical connection diagrams. Please be aware that
the CS4923/4/5/6/7/8/9 symbol may appear with code and is running an application, however,
differently in each diagram.
pin 20 is called INTREQ. INTREQ is an open drain
output used to inform the host that the DSP has an
outgoing message which should be read.
The external memory interface is only supported
when a serial communication mode has been
chosen.
In this document, pins will be referred to by their
functionality. The section “Pin Descriptions” on
page 49 describes each pin of the CS492X and lists
all of its names. Please refer to the Pin Descriptions
section when exact pin numbers are in question.
The typical connection diagrams demonstrate the
PLL being used (CLKSEL is pulled low). To
enable external CLKIN, CLKSEL should be pulled
high. The system designer must be aware that
certain software features may not be available if The device has 12 general purpose input and output
external CLKIN is used as the DSP must run
slower when external CLKIN is used. The system
designer should also be aware of additional duty
(GPIO[11:0]) pins that all have multiple
functionality. While in one of the parallel
communication modes (see section 6.2), these pins
cycle requirements when using external CLKIN are used to implement the parallel host
mode. It is highly suggested that the system
designer take advantage of the PLL and pull
CLKSEL low.
communication interface. While in one of the serial
host modes these pins are used to implement an
external memory interface. Alternatively while in
one of the serial host modes these pins could be
used for another general purpose if the application
code has been programmed to support the special
purpose. In this document the pins are referenced
by the name corresponding to their particular use.
Sometimes GPIO[11:0], or some subset thereof, is
used when referring to the pins in a general sense.
3.1 Multiplexed Pins
The CS4923/4/5/6/7/8/9 family of digital signal
processors (DSPs) incorporate a large amount of
flexibility into a 44 pin package. Because of the
high degree of integration, many of these pins are
internally multiplexed to serve multiple purposes.
DS262F2
23
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