CS4351
least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and 36 cycles
in format 5.
LR C K
Left C ha nnel
R ig ht C ha nnel
S C LK
SDIN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 5. Left-Justified up to 24-Bit Data
LR C K
Left Channel
R ight C ha nnel
S C LK
SDIN
M SB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 6. I²S, up to 24-Bit Data
LRCK
Left Channel
R ight Cha nnel
SCLK
SDIN
M SB
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LSB
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
LSB
Figure 7. Right-Justified Data
4.4
De-Emphasis Control
The device includes on-chip digital de-emphasis.
shows the de-emphasis curve for F
s
equal to 44.1
kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample
rate, Fs.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 8. De-Emphasis Curve
Note:
DS566F1
De-emphasis is only available in Single-Speed Mode.
17
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