CS4349
8. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
8.1
Device and Revision ID - Register 01h
7
6
Device3
1
5
Device2
1
4
Device1
1
3
2
Rev2
-
1
Rev1
-
0
Rev0
-
Device4
1
Device0
-
Function:
This register is Read-Only. It is decoded as follows:
Rev
A
Register 01h contents
1111,0000
B
1111,0001
C2
1111,1111
8.2
Mode Control - Register 02h
7
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
2
1
FM1
0
0
FM0
0
Reserved
0
DEM1
0
DEM0
0
8.2.1
Digital Interface Format (DIF[2:0]) Bits 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 11-13.
DIF2
DIF1
DIF0
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
TDM slot 0
TDM slot 1
TDM slot 2
TDM slot 3
Format
0 (Default)
Figure
11
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
12
13
13
15
15
15
15
Table 3. Digital Interface Formats
DS782F1
29
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