CS4297
CrystalClear™ SoundFusion™ Audio Codec ’97
SERIAL PORT TIMING (Continued)
Misc. Timing Parameters
Ts2_pdown
Tsync_pr4
Tsync2clk
Tsetup2rst
Toff
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4)
-
1.0
162.8
15
16.24
16.36
µs
µs
ns
ns
ns
-
-
-
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (test modes)
Rising edge of RESET# to Hi-Z delay
244
(Note 4)
(Note 4)
-
-
-
-
25
BIT_CLK
RESET#
T
T
rst2clk
rst_low
T
vdd2rst#
Vdd
T
rst2sync
SYNC
Power Up Timing
BIT_CLK
T
T
ifall
orise
T
T
T
clk_period
clk_high clk_low
SYNC
T
T
ifall
irise
T
T
sync_low
sync_high
T
sync_period
Clocks
BIT_CLK
SYNC
T
sync2crd
CODEC_READY
Codec Ready from Startup or Fault Condition
8
DS242F5
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