CS4297
CrystalClear™ SoundFusion™ Audio Codec ’97
DIGITAL CHARACTERISTICS (AVss = DVss = 0 V (See Grounding and Layout section))
Parameter
Symbol
Min
Typ
Max
Unit
V
Vil
Low level input voltage
-
-
-
0.16 x DVdd
Vih
Voh
Vol
High level input voltage
High level output voltage
0.40 x DVdd
-
-
V
0.70 x DVdd 0.99 x DVdd
V
Low level output voltage
-
-10
-10
-
0.03
0.10 x DVdd
V
Input Leakage Current (AC-link inputs)
Output Leakage Current (Tri-stated AC-link outputs)
-
-
10
10
µA
µA
µA
Output buffer drive current
(Note 4)
100
400
SERIAL PORT TIMING
Parameter
Symbol
Min
Typ
Max
Unit
RESET Timing
DVdd 90% maximum value to RESET# inactive pre-delay
(Note 4)
TVdd2rst#
Trst_low
Trst2clk
1.5
1.0
-
-
-
-
-
-
ms
µs
RESET# active low pulse width
-
RESET# inactive to BIT_CLK start-up delay
42.7
40.6
ms
µs
Tsync2crd
1st SYNC active to CODEC READY set
Clocks
-
BIT_CLK frequency
-
12.288
-
MHz
Tclk_period
BIT_CLK period
-
-
81.4
-
-
ns
ps
BIT_CLK output jitter (depends on XTAL_IN source)
750
Tclk_high
Tclk_low
BIT_CLK high pulse width
-
40.7
-
ns
BIT_CLK low pulse width
SYNC frequency
-
-
40.7
48
-
-
ns
kHz
Tsync_period
Tsync_high
Tsync_low
Trst2snyc
SYNC period
-
-
-
-
20.8
1.3
19.5
-
-
µs
µs
µs
ms
SYNC high pulse width
SYNC low pulse width
-
-
SYNC active to RESET# inactive pre-delay
250
Data Setup and Hold
Tprop
Tohold
Tisetup
Tihold
Tirise
Tifall
Output Propagation delay from rising edge of BIT_CLK
Output hold from falling edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input Signal rise time
-
5
6
-
8
-
ns
ns
ns
ns
ns
ns
ns
ns
10
0
-
-
-
-
2
-
6
6
6
6
Input Signal fall time
2
-
Tofall
Output Signal rise time
Output Signal fall time
(Note 4)
(Note 4)
2
4
4
Tofall
2
DS242F5
7
CIRRUS [ CIRRUS LOGIC ]
