CS4297
CrystalClear™ SoundFusion™ Audio Codec ’97
PIN DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
DVdd1
XTL_IN
L
I
N
E
_
O
UT_R
1
36
35
34
33
32
31
30
29
28
27
26
25
LINE_OUT_L
2
XTL_OUT
DVss1
NC
NC
NC
NC
3
4
SDATA_OUT
BIT_CLK
5
6
AFLT2
AFLT1
DVss2
SDATA_IN
DVdd2
7
8
Vrefout
REFFLT
AVss1
9
SYNC
10
11
12
RESET#
PC_BEEP
AVdd1
13 14 15 16 17 18 19 20 21 22 23 24
Digital I/O Pins
RESET# - AC’97 Chip Reset, Input
This active low signal is the asynchronous Cold Reset input to the CS4297. The CS4297 must
be reset before it can enter normal operating mode.
SYNC - AC-link Serial Port Sync pulse, Input
This signal is the serial port timing signal for the AC-link of the CS4297. Its period is the
reciprocal of the sample rate of the CS4297, 48 kHz. This signal is generated by the AC’97
Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the
CS4297 is in a Warm Reset state. A series terminating resistor of 47 Ω should be connected on
this signal close to the device driving the signal.
BIT_CLK - AC-link Serial Port Master Clock, Output
This output signal controls the master clock timing for the AC-link. It is a 12.288 MHz clock
signal which is divided down by two from the XTL_IN input clock. A series terminating
resistor of 47 Ω should be connected on this signal close to the CS4297.
DS242F5
39
CIRRUS [ CIRRUS LOGIC ]
