CS4297A
CS4297A
SDATA_OUT in their normal capacities. Either a
Cold Reset or a Warm Reset is required to restore
operation to the CS4297A. A Cold Reset will re-
store all mixer registers to their power-on default
values. A Warm Reset will not alter the values of
any mixer register, except clearing the PR4 bit in
Powerdown Control/Status Register (Index 26h).
5.2
Powerdown Controls
Powerdown Control/Status
The
Register
(Index 26h) controls the power management func-
tions. The PR[6:0] bits in this register control the
internal powerdown states of the CS4297A. Power-
down control is available for individual subsections
of the CS4297A by asserting any PRx bit or any
combination of PRx bits. Most powerdown states
can be resumed by clearing the corresponding PRx
bit. Table 10 shows the mapping of the power con-
trol bits to the functions they manage.
The PR5 bit powers down all analog and digital
subsections of the device. A Cold Reset is the only
way to restore operation to the CS4297A after a
PR5 global powerdown.
When PR0 is ‘set’, the L/R ADCs and the Input
Mux are shut down and the ADC bit in the Power-
down Control/Status Register (Index 26h) is
‘cleared’ indicating the ADCs are no longer in a
ready state. The same is true for the DACs, the an-
alog mixers, and the reference voltage (Vrefout).
When the PR2 or PR3 bit of the mixer is ‘cleared’,
the mixer section will begin a power-on process,
and the corresponding powerdown status bit will be
‘set’ when the hardware is ready.
The CS4297A does not automatically mute any in-
put or output when the powerdown bits are ‘set’.
The software driver controlling the AC ’97 device
must manage muting the input and output analog
signals before putting the part into any power man-
agement state. The definition of each PRx bit may
affect a single subsection or a combination of sub-
sections within the CS4297A. Table 11 on page 34
contains the matrix of subsections affected by the
respective PRx function. Table 12 on page 34
shows the different operating power consumptions
levels for different powerdown functions.
Shutting down the AC-link by ‘setting’ PR4 causes
the primary Codec to turn off the BIT_CLK and
drive SDATA_IN low. It also ignores SYNC and
PR Bit
Function
PR0
PR1
PR2
PR3
PR4
PR5
PR6
L/R ADCs and Input Mux Powerdown
Front DACs Powerdown
Analog Mixer Powerdown (Vref on)
Analog Mixer Powerdown (Vref off)
AC-link Powerdown (BIT_CLK off)*
Internal Clock Disable
Alternate Line Out Powerdown
* Applies only to primary codec
Table 10. Powerdown PR Bit Functions
DS318PP6
33
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