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CS42438-CMZ 参数 Datasheet PDF下载

CS42438-CMZ图片预览
型号: CS42438-CMZ
PDF下载: 下载PDF文件 查看货源
内容描述: 108分贝192千赫6英寸,8出TDM CODEC [108 dB, 192 kHz 6-in, 8-out TDM CODEC]
分类和应用: 消费电路商用集成电路
文件页数/大小: 64 页 / 1066 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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2 PIN DESCRIPTIONS - HARDWARE MODE  
52 51 50 49 48 47 46 45 44 43 42 41 40  
AIN5_MUX  
AIN6_MUX  
AIN1+  
AIN1-  
39  
38  
1
2
VA  
MFREQ  
3
37  
36  
35  
34  
33  
ADC3_HPF  
VQ  
4
AGND  
AOUT8-  
AOUT8+  
AOUT7+  
AOUT7-  
AOUT6-  
AOUT6+  
AOUT5+  
RST  
VLC  
5
6
CS42438  
FS  
7
VD  
8
32  
31  
30  
29  
28  
27  
DGND  
VLS  
9
10  
11  
12  
SCLK  
MCLK  
ADC_SDOUT/  
ADC3_SINGLE  
AOUT5-  
13  
14 15 16 17 18 19 20 21 22 23 24 25 26  
Pin Name  
#
Pin Description  
AIN5_MUX  
AIN6_MUX  
1
2
Analog Input Multiplexer (Input) - Allows selection between the A and B single-ended inputs of  
ADC3. See sections 7.6.7 and 7.6.8 for details.  
3
MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock. See sec-  
tion 5.4 for the appropriate settings.  
MFREQ  
4
ADC3 High-Pass Filter Freeze (Input) - When this pin is driven high, the internal high-pass filter  
will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted  
from the conversion result. See “ADC Digital Filter Characteristics” on page 15.  
ADC3_HPF  
RST  
VLC  
5
6
Reset (Input) - The device enters a low power mode and all internal registers are reset to their  
default settings when low.  
Control Port Power (Input) - Determines the required signal level for the control port interface.  
See “Digital I/O Pin Characteristics” on page 7.  
FS  
7
8
Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format.  
Digital Power (Input) - Positive power supply for the digital section.  
VD  
VLS  
10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-  
faces.  
SCLK  
11  
Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs.  
ADC_SDOUT/  
ADC3_SINGLE  
13 Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data. Start-up  
Option for Hardware Mode: Pull-up to VLS enables Single-Ended Mode for AIN5-AIN6.  
DAC_SDIN  
AUX_LRCK  
14 DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.  
15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active  
on the Auxiliary serial audio data line.  
8
DS646PP2