CS42426
When the device is clocked from OMCK, the frequency of OMCK must be at least twice the frequency of
the fastest Slave Mode, SCLK. For example, if both serial ports are in Slave Mode with one SCLK running
at 32x Fs and the other at 64x Fs, the slowest OMCK signal that can be used to clock the device is
128x Fs.
When either serial port is in Slave Mode, its respective LRCK signal must be present for proper device
operation.
In Slave Mode, One-Line Mode #1 is supported; One-Line Mode #2 is not.
The sample rate to OMCK ratios and OMCK frequency requirements for Slave Mode operation are shown
in Table 1. Refer to Table 3 for required clock ratios.
Single-Speed
256x, 384x, 512x
32x, 48x, 64x, 128x
Double-Speed
128x, 192x, 256x
32x, 48x, 64x
Quad-Speed
64x, 96x, 128x
32x, 48x, 64x
One-Line Mode #1
OMCK/LRCK Ratio
SCLK/LRCK Ratio
256x
128x
Table 3. Slave Mode Clock Ratios
4.5
Digital Interfaces
Serial Audio Interface Signals
4.5.1
The CS42426 interfaces to an external Digital Audio Processor via two independent serial ports, the
DAC serial port, DAC_SP, and the ADC serial port, ADC_SP. The digital output of the internal ADCs use
the ADC_SDOUT pin and can be configured to use either the ADC or DAC serial port timings.These con-
figuration bits and the selection of Single-, Double- or Quad-Speed Mode for DAC_SP and ADC_SP are
found in register “Functional Mode (address 03h)” on page 43.
The serial interface clocks, ADC_SCLK for ADC_SP and DAC_SCLK for DAC_SP, are used for transmit-
ting and receiving audio data. Either ADC_SCLK or DAC_SCLK can be generated by the CS42426 (Mas-
ter Mode), or it can be input from an external source (Slave Mode). Master or Slave Mode selection is
made using bits DAC_SP M/S and ADC_SP M/S in register “Misc Control (address 05h)” on page 46.
The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the
start of a new sample period. It may be an output of the CS42426 (Master Mode), or it may be generated
by an external source (Slave Mode). As described in later sections, particular modes of operation do allow
the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other.
The serial data interface format selection (Left/Right-Justified, I²S or One-Line Mode) for the ADC serial
port data out pin, ADC_SDOUT, and the DAC input pins, DAC_SDIN1:3, is configured using the appro-
priate bits in the register “Interface Formats (address 04h)” on page 45. The serial audio data is presented
in two's complement binary form with the MSB first in all formats.
DAC_SDIN1, DAC_SDIN2, and DAC_SDIN3 are the serial data input pins supplying the internal DAC.
ADC_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs and, when config-
ured for one-line mode, up to four additional ADC channels attached externally to the signals ADCIN1 and
ADCIN2 (typically two CS5361 stereo ADCs). When operated in One-Line Mode, 6 channels of DAC data
are input on DAC_SDIN1 and 6 channels of ADC data are output on ADC_SDOUT. Table 4 on page 26
outlines the serial port channel allocations.
DS604F1
25
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