CS42406
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE Inputs: Logic
0 = GND, Logic 1 = VLC
Parameter
Symbol
Min
Max
Unit
I²C Mode
SCL Clock Frequency
f
-
100
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
scl
t
500
4.7
4.0
4.7
4.0
4.7
0
-
DAC_RST Rising Edge to Start
irs
Bus Free Time Between Transmissions
t
-
buf
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
t
-
hdst
t
-
low
Clock High Time
t
-
high
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
t
-
sust
(Note 19)
t
-
hdd
t
250
-
-
sud
t , t
1
rc rc
Fall Time SCL and SDA
t , t
-
300
-
fc fc
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
t
4.7
-
susp
(Note 20)
t
(Note 21)
ack
Notes: 19. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
5
5
5
21.
for Single-Speed Mode,
for Double-Speed Mode,
for Quad-Speed Mode.
----------------------
----------------------
-------------------
256 × Fs
128 × Fs
64 × Fs
DAC_RST
t
irs
Repeated
Start
Stop
Start
Stop
t
t
rd
fd
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
fc
susp
hdst
low
t
t
t
t
t
t
sust
sud
ack
rc
hdd
Figure 31. Control Port Timing - I²C Mode
27
CIRRUS [ CIRRUS LOGIC ]
