CS42325
6.6.2
6.6.3
ADC Serial Port Source
This bit selects which serial port provides the sub clocks for the ADC.
ADC_SP
ADC sub clock source
0
1
Serial Port 1 (SCLK1/LRCK1)
Serial Port 2 (SCLK2/LRCK2)
ADC Digital Interface Format (ADC_DIF)
These bits configure the serial audio interface format for transmitting digital audio data on SDOUT
ADC_DIF[1:0] ADC Serial Audio Interface Format
00
Left-Justified, 24-bit data
I²S, 24-bit data
Reserved
01
10
11
Reserved
6.7
DAC1 Clocking (Address 07h)
7
6
5
4
3
2
1
0
Reserved
DAC1_MCLK
Reserved
DAC1_SP
Reserved
Reserved
DAC1_DIF1
DAC1_DIF0
6.7.1
6.7.2
6.7.3
DAC1 MCLK Source
This bit selects which MCLK pin provides the clock for DAC1.
DAC1_MCLK DAC1 MCLK source
0
1
MCLK1
MCLK2
DAC1 Serial Port Source
This bit selects which serial port provides the sub clocks for the DAC1.
DAC1_SP DAC1 sub clock source
0
1
Serial Port 1 (SCLK1/LRCK1)
Serial Port 2 (SCLK2/LRCK2)
DAC1 Digital Interface Format (DAC1_DIF)
These bits configure the serial audio interface format for incoming digital audio data on SDIN1.
DAC1_DIF[1:0]
00
DAC1 Serial Audio Interface Format
Left-Justified, up to 24-bit data
01
10
11
I²S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
DS838A2
51
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