CS42325
6.3.6
Tri-State Serial Port 2
When enabled, and the device is configured as a master, then SCLK2 and LRCK2 of Serial Port 2 (SP2)
will be placed in a high-impedance output state. If Serial Port 2 is configured as a slave, SCLK2 and
LRCK2 will remain as inputs. SDIN1 and SDIN2 are always configured as inputs.
TRI-SP2
SCLK2 and LRCK2 State
0
1
SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2
operate as outputs if Serial Port 2 is configured as a master
SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2
become high-impedance outputs if Serial Port 2 is configured as a master
6.4
Serial Port 1 Control (Address 03h)
7
6
5
4
3
2
1
0
MCLK1
FREQ1
MCLK1
FREQ0
SP1_M/S
Reserved
Reserved
SP1_SPEED
Reserved
SP1_MCLK
6.4.1
6.4.2
6.4.3
Serial Port 1 Master/Slave Select
This bit configures Serial Port 1 to operate as either a clock master or clock slave.
SP1_M/S Serial Port 1 Master/Slave Select
0
1
Slave Mode
Master Mode
Serial Port 1 Speed Mode
In Master Mode this bit configures the speed mode of Serial Port 1.
SP1_SPEED Serial Port 1 Speed Mode
0
1
Single-Speed Mode (SSM)
Double-Speed Mode (DSM)
MCLK1 Divider
These bits configure the internal MCLK1 dividers.
MCLK1
MCLK Divider
FREQ[1:0]
00
01
10
11
÷1
÷1.5
÷2
÷3
6.4.4
Serial Port 1 MCLK source
This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 1.
SP1_MCLK Serial Port 1 MCLK source
0
1
MCLK1
MCLK2
DS838A2
49
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