CS4226
SWITCHING CHARACTERISTICS - CONTROL PORT
(Inputs: logic 0 = DGND, logic 1 =
VD+, C
L
= 30 pF)
Parameter
Symbol
f
sck
t
csh
t
css
t
scl
t
sch
t
dsu
(Note 12)
t
dh
t
pd
t
r1
t
f1
(Note 13)
(Note 13)
t
r2
t
f2
Min
-
1.0
20
66
66
40
15
45
25
25
100
100
Max
6
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPI Mode
(SPI/I
2
C = 0)
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Notes: 12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For F
SCK
< 1 MHz
CS
t css
CCLK
t
r2
CDIN
t scl
t
sch
t csh
t
f2
t dsu t
dh
CDOUT
t
pd
8
DS188F4
CIRRUS [ CIRRUS LOGIC ]
