CS4226
The analog signal is input to the mono ADC via
the AINAUX pin.
sample rate of 44.1 kHz. This filter response
scales linearly with sample rate.
Independent Muting of both the stereo ADC's
and the mono ADC is possible through the
ADC Control Byte with the MUTR, MUTL and
MUTM bits.
Frequency Response
-3 dB @ 3.4 Hz
-0.13 dB @ 20 Hz
10 degrees @ 20 Hz
None
Phase Deviation
Passband Ripple
Table 3. High Pass Filter Characteristics
2.2.2 Adjustable Input Gain
2.3 Analog Outputs
The signals from the line inputs are routed to a
programmable gain circuit which provides up
to 9 dB of gain in 3 dB steps. The gain is ad-
justable through the Input Control Byte. Right
and left channel gain settings are controlled in-
dependently with the GNR1/0 and GNL1/0
bits. Level changes occur immediately on reg-
ister updates. To minimize audible artifacts,
level changes should be done with the channel
muted.
2.3.1 Line Level Outputs
The CS4226 contains an on-chip buffer ampli-
fier producing single-ended outputs capable of
driving 10 kΩ loads. Each output (A
1-6)
OUT
will produce a nominal 2.83 Vpp (1 Vrms) out-
put with a 2.3 volt quiescent voltage for a full
scale digital input. The recommended off-chip
analog filter is a 2nd order Butterworth with a
-3 dB corner at Fs, see Figure 3. This filter pro-
vides out-of-band noise attenuation along with
a gain of 2, providing a 2 Vrms output signal. A
3rd order Butterworth filter with a -3 dB corner
at 0.75 Fs can be used if greater out of band
noise filtering is desired. The CS4226 DAC in-
terpolation filter is a linear phase design which
has been pre-compensated for an external
2nd order Butterworth filter to provide a flat fre-
quency response and linear phase response
over the passband. If this filter is not used,
small frequency response magnitude and
phase errors will occur.
The ADC Status Report Byte provides feed-
back of input level for each ADC channel. This
register continuously monitors the ADC output
and records the peak output level since the
last register read. Reading this register causes
it to reset to 0 and peak monitoring begins
again.
2.2.3 High Pass Filter
The operational amplifiers in the input circuitry
driving the CS4226 may generate a small DC
offset into the A/D converter. The CS4226 in-
cludes a high pass filter after the decimator to
remove any DC offset which could result in re-
cording a DC level, possibly yielding “clicks”
when switching between devices in a multi-
channel system.
2.3.2 Output Level Attenuator
The DAC outputs are each routed through an
attenuator which is adjustable in 1 dB steps.
Output attenuation is available through the
Output Attenuator Data Bytes. Level changes
are implemented in the analog domain such
that the noise is attenuated by the same
amount as the signal, until the residual output
noise is equal to the noise floor in the mute
state; at this point attenuation is implemented
The characteristics of this first-order high pass
filter are outlined Table 3 below for an output
12
DS188F4
CIRRUS [ CIRRUS LOGIC ]
