CS4225
SWITCHING CHARACTERISTICS - CONTROL PORT
Parameter
SPI Mode
(H/S=0)
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to SCK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
CDIN (Note 9)
fsck
tcsh
tcss
tscl
tsch
tdsu
tdh
tpd
tr1
tf1
tr2
tf2
Symbol
(T
A
= 25
o
C VD+, VA+ = 5V±10%; Inputs: logic 0 = DGND, logic 1 = VD+, C
L
= 30pF)
Min
Max
Units
0
1.0
20
500
500
250
50
1
MHz
µs
ns
ns
ns
ns
ns
250
25
25
100
100
ns
ns
ns
ns
ns
Notes: 9. Data must be held for sufficient time to bridge the transition time of CCLK.
CS
t css
CCLK
t r2
CDIN
t dsu
CDOUT
t f2
t scl
t sch
t csh
t dh
t pd
6
DS86PP8
CIRRUS [ CIRRUS LOGIC ]
