CS4223 CS4224
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224)
(TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency
fsck
tsrs
tspi
tcsh
tcss
tscl
tsch
tdsu
tdh
-
41
500
1.0
20
66
66
40
15
-
6
MHz
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
RST rising edge to CS falling
CCLK edge to CS falling
CS High Time between transmissions
CS falling to CCLK edge
CCLK Low Time
(Note 11)
(Note 12)
-
-
-
-
-
CCLK High Time
-
-
CDIN to CCLK rising setup time
CCLK rising to DATA hold time
Rise time of CCLK and CDIN
Fall time of CCLK and CDIN
(Note 13)
(Note 14)
(Note 14)
-
tr2
100
100
tf2
-
Notes: 11. Not tested but guaranteed by design.
12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For FSCK < 1 MHz.
RST
CS
t
t
srs
spi
t
t
t
css
scl
sch
t
csh
CCLK
t
t
r2
f2
CDIN
t
t
dsu
dh
Figure 2. SPI Control Port Timing
8
DS290PP3
CIRRUS [ CIRRUS LOGIC ]
